CY7C68013A-56LFXCT Cypress Semiconductor Corp, CY7C68013A-56LFXCT Datasheet - Page 24
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CY7C68013A-56LFXCT
Manufacturer Part Number
CY7C68013A-56LFXCT
Description
CY7C68013A-56LFXCT
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Datasheet
1.CY7C68013A-56PVXC.pdf
(62 pages)
Specifications of CY7C68013A-56LFXCT
Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, USART, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
Lead Free Status / Rohs Status
Details
Table 11. FX2LP Pin Descriptions (continued)
Document #: 38-08032 Rev. *M
TQFP
PORT C
PORT D
128
102
103
55
56
57
72
73
74
75
76
77
78
79
TQFP
100
45
46
47
57
58
59
60
61
62
63
64
80
81
SSOP
56
30
31
32
52
53
QFN
56
23
24
25
45
46
56 VF-
BGA
5G
6H
8A
7A
5F
PB5 or
FD[5]
PB6 or
FD[6]
PB7 or
FD[7]
PC0 or
GPIFADR0
PC1 or
GPIFADR1
PC2 or
GPIFADR2
PC3 or
GPIFADR3
PC4 or
GPIFADR4
PC5 or
GPIFADR5
PC6 or
GPIFADR6
PC7 or
GPIFADR7
PD0 or
FD[8]
PD1 or
FD[9]
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Default
(PB5)
(PB6)
(PB7)
(PC0)
(PC1)
(PC2)
(PC3)
(PC4)
(PC5)
(PC6)
(PC7)
(PD0)
(PD1)
I
I
I
I
I
I
I
I
I
I
I
I
I
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by
PORTCCFG.0
PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.1
PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.2
PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.3
PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.4
PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.5
PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.6
PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.7
PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
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Page 24 of 62
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