CY7C68013A-56LFXCT Cypress Semiconductor Corp, CY7C68013A-56LFXCT Datasheet - Page 7

• Manufacturer Part Number: CY7C68013A-56LFXCT
• Description: CY7C68013A-56LFXCT
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-56LFXCT

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Details

Table 5. Reset Timing Values
3.9.2 Wakeup Pins
The 8051 puts itself and the rest of the chip into a power down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic the oscillator
restarts after the PLL stabilizes, and the 8051 receives a wakeup
interrupt. This applies whether or not FX2LP is connected to the
USB.
The FX2LP exits the power down (USB suspend) state using one
of the following methods:
■
■
■
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This enables a simple external R-C
network to be used as a periodic wakeup source. WAKEUP is by
default active LOW.
Document #: 38-08032 Rev. *M
Power on Reset with Crystal
Power on Reset with External
Clock
Powered Reset
USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX2LP and initiate a wakeup)
External logic asserts the WAKEUP pin
External logic asserts the PA3/WU2 pin
RESET#
VCC
Condition
T
Power on Reset
RESET
200 μs + Clock stability time
T
200 μs
5 ms
RESET
Figure 2. Reset Timing Plots
V
3.3V
3.0V
0V
IL
RESET#
3.10 Program/Data RAM
3.10.1 Size
The FX2LP has 16 KBytes of internal program/data RAM, where
PSEN#/RD# signals are internally ORed to enable the 8051 to
access it as both program and data memory. No USB control
registers appear in this space.
Two memory maps are shown in the following diagrams:
Figure 3
Figure 4
3.10.2 Internal Code Memory, EA = 0
This mode implements the internal 16 KByte block of RAM
(starting at 0) as combined code and data memory. When
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside the
chip. This enables the user to connect a 64 KByte memory
without requiring address decodes to keep clear of internal
memory spaces.
Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM
spaces have the following access:
■
■
■
■
3.10.3 External Code Memory, EA = 1
The bottom 16 KBytes of program memory is external and
therefore the bottom 16 KBytes of internal RAM is accessible
only as a data memory.
VCC
USB download
USB upload
Setup data pointer
I
2
C interface boot load.
on page 8 shows the Internal Code Memory, EA = 0
on page 9 shows the External Code Memory, EA = 1.
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
T
RESET
Powered Reset
Page 7 of 62
3.3V
0V
V
IL
[+] Feedback