CY8CTMG200-32LQXIT Cypress Semiconductor Corp, CY8CTMG200-32LQXIT Datasheet - Page 121

• Manufacturer Part Number: CY8CTMG200-32LQXIT
• Description: CY8CTMG200-32LQXIT
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-32LQXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The following diagram illustrates an example of how the address pointers are configured in EZI2C mode. In this example, the
external master sent a Start, Slave Address, and a data byte of 2 to initialize both the base address pointer (I2C_BP register)
and the current address pointer (I2C_CP register). Then, 4 bytes were written, OR a Start or Restart was sent with the device
address, and 4 bytes were read. On the CPU side, a 2 was written to the CPU base address register (CPU_BP register), and
6 subsequent bytes were read from or written to the I2C_BUFF register by the CPU.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Bytes from I2C
Receive Data
Transmit Data
Bytes to I2C
Interface
Interface
I2C Current Pointer
I2C Base Pointer
(I2C_BP)
(I2C_CP)
2
6
Figure 15-5. Address Pointer in EZI2C Mode
Buffer Module
32-Byte
RAM
0
1
2
3
4
5
6
7
8
9
CPU Base Pointer
CPU Current Pointer
(CPU_BP)
(CPU_CP)
2
8
Bytes from CPU
(CPU Read from
Transmit Data
(CPU Write to
Receive Data
Bytes to CPU
I2C_BUFF)
I2C_BUFF)
I2C Slave
121
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