CY8CTST200A-48PVXIT Cypress Semiconductor Corp, CY8CTST200A-48PVXIT Datasheet - Page 178
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CY8CTST200A-48PVXIT
Manufacturer Part Number
CY8CTST200A-48PVXIT
Description
CY8CTST200A-48PVXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200A-48PVXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
38
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Processor Series
CY8CTxx2xxA
Core
M8C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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20.3.11
The PSoC Memory Arbiter Write Address Register
(PMAx_WA) is used to set the beginning SRAM address for
the PMA channel. A PMAx_WA register address uses the
same physical register as the PMAx_RA register address.
Therefore, when the read address is changed, the write
address is also changed and the PMAx_RA and PMAx_WA
registers always return the same value when read.
Full-Speed USB
178
1,34h
1,35h
1,36h
1,37h
1,38h
1,39h
1,3Ah
1,3Bh
1,44h
1,45h
1,46h
1,47h
1,48h
1,49h
1,4Ah
1,4Bh
Address
PMA0_WA
PMA1_WA
PMA2_WA
PMA3_WA
PMA4_WA
PMA5_WA
PMA6_WA
PMA7_WA
PMA8_WA
PMA9_WA
PMA10_WA
PMA11_WA
PMA12_WA
PMA13_WA
PMA14_WA
PMA15_WA
PMAx_WA Register
Name
Bit 7
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Bit 5
Bit 4
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Write Address[7:0]
Bits 7 to 0: Address[7:0]. The value returned when this
register is read depends on whether the PMA channel is
being used by the USB SIE or by the M8C. In the USB case,
this register always returns the beginning SRAM address for
the PMA channel. In the M8C case, this register always
returns the next SRAM address that is used by the PMA
channel, if a byte is written to the channel's data register
(PMAx_DR) by the M8C.
For additional information, refer to the
page
263.
Bit 3
Bit 2
Bit 1
PMAx_WA register on
Bit 0
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
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