CYWUSB6935-48LTXC Cypress Semiconductor Corp, CYWUSB6935-48LTXC Datasheet - Page 9
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CYWUSB6935-48LTXC
Manufacturer Part Number
CYWUSB6935-48LTXC
Description
CYWUSB6935-48LTXC
Manufacturer
Cypress Semiconductor Corp
Specifications of CYWUSB6935-48LTXC
Frequency
2.4GHz
Data Rate - Maximum
62.5kbps
Modulation Or Protocol
DSSS, GFSK
Applications
AMR, ISM, RKE
Power - Output
0dBm
Sensitivity
-95dBm
Voltage - Supply
2.7 V ~ 3.6 V
Current - Receiving
57.7mA
Current - Transmitting
69.1mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Product Depth (mm)
7mm
Product Length (mm)
7mm
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CYWUSB6935-48LTXC
Manufacturer:
ST
Quantity:
1 200
Table 6. Data Rate
Note
■ 001–Not Valid
■ 010–Not Valid
■ 011–Not Valid
■ 111–Not Valid
Document #: 38-16008 Rev. *E
2. The following Reg 0x04, bits 2:0 values are not valid:
7:3 Reserved
2
1
0
Bit
[2]
[2]
[2]
Code Width The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes.
Data Rate
Sample
Rate
7
Name
Addr: 0x04
These bits are reserved and should be written with zeroes.
1 = 32 chips/bit PN codes
0 = 64 chips/bit PN codes
The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to
interference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when
double data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well as
more robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits are
impacted and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit 1),
and Sample Rate (Reg 0x04, bit 0).
of 62.5kbits/sec.
1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions)
0 = Normal Data Rate - 1 bit per PN code
This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit
(Reg 0x04, bit 2=1). When using Double Data Rate, the raw data throughput is 62.5 kbits/sec because every 32
chips/bit PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is placed
in the PN code register. This 64 chips/bit PN code is then split into two and used by the baseband to offer the
Double Data Rate capability. When using Normal Data Rate, the raw data throughput is 32 kbits/sec. Additionally,
Normal Data Rate enables the user to potentially correlate data using two differing 32 chips/bit PN codes.
The Sample Rate bit allows the use of the 12x sampling when using 32 chips/bit PN codes and Normal Data Rate.
1 = 12x Oversampling
0 = 6x Oversampling
Using 12x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or Double
Data Rate this bit is don’t care. The only time when 12x oversampling can be selected is when a 32 chips/bit PN
code is being used with Normal Data Rate.
The Data Rate bit allows the user to select Double Data Rate mode of operation which delivers a raw data rate
6
Reserved
5
REG_DATA_RATE
4
Description
3
Code Width
2
Data Rate
1
CYWUSB6935
Default: 0x00
Sample Rate
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