DSPIC33FJ128GP804-H/PT Microchip Technology, DSPIC33FJ128GP804-H/PT Datasheet - Page 195

• Manufacturer Part Number: DSPIC33FJ128GP804-H/PT
• Description: 16-bit DSC, 128KB Flash, CAN, DMA, 40 MIPS, NanoWatt 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP804-H/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-TQFP
• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 140 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.0
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices support
up to four input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
FIGURE 14-1:
© 2011 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Note 1: This data sheet summarizes the features
ICx pin
2: Some registers and associated bits
INPUT CAPTURE
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
of
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 12. Input Capture”
(DS70198) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to
“Memory Organization”
sheet for device-specific register and bit
information.
the
from
INPUT CAPTURE BLOCK DIAGRAM
the
dsPIC33FJ32GP302/304,
Falling Edge Mode
(16th Rising Edge)
Rising Edge Mode
(4th Rising Edge)
Prescaler Mode
Prescaler Mode
Edge Detection
Wake-up Mode
Sleep/Idle
Microchip
Mode
in this data
Section 4.0
website
and
101
100
011
010
001
ICM<2:0>
CaptureEvent
1.
2.
3.
Each input capture channel can select one of two 16-
bit timers (Timer2 or Timer3) for the time base. The
selected timer can use either an internal or external
clock.
Other operational features include:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Use of input capture to provide additional sources
ICTMR
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
of external interrupts
Note:
Simple Capture Event modes:
- Capture timer value on every falling edge of
- Capture timer value on every rising edge of
Capture timer value on every edge (rising and
falling)
Prescaler Capture Event modes:
- Capture timer value on every 4th rising
- Capture timer value on every 16th rising
4 buffer locations are filled
input at ICx pin
input at ICx pin
edge of input at ICx pin
edge of input at ICx pin
FIFO CONTROL
TMR2 TMR3
ICxBUF
ICI<1:0>
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to ‘1’ (ICI<1:0> = 00)
/N
FIFO
ICM<2:0>
001
111
To CPU
(In IFSx Register)
Set Flag ICxIF
DS70292E-page 195