DSPIC33FJ128GP804T-I/PT Microchip Technology, DSPIC33FJ128GP804T-I/PT Datasheet - Page 79
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DSPIC33FJ128GP804T-I/PT
Manufacturer Part Number
DSPIC33FJ128GP804T-I/PT
Description
16-bit DSC, 128KB Flash,CAN,DMA,40 MIPS,nanoWatt 44 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128GP804T-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b, D/A 6x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ128GP804T-I/PTTR
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP804T-I/PT
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Quantity:
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6.0
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
FIGURE 6-1:
© 2011 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
RESETS
of
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 8. Reset” (DS70192) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to
“Memory Organization”
sheet for device-specific register and bit
information.
MCLR
V
DD
the
Uninitialized W Register
Configuration Mismatch
RESET SYSTEM BLOCK DIAGRAM
Regulator
RESET Instruction
Internal
Sleep or Idle
dsPIC33FJ32GP302/304,
Module
Illegal Opcode
WDT
Trap Conflict
V
in this data
Detect
DD
Section 4.0
Glitch Filter
Rise
and
BOR
POR
A simplified block diagram of the Reset module is
shown in
Any active source of reset will make the SYSRST sig-
nal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Register
Figure
Refer to the specific peripheral section or
Section 3.0 “CPU”
register Reset states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
6-1).
6-1.
SYSRST
of this manual for
DS70292E-page 79
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