DSPIC33FJ128MC202-E/MM Microchip Technology, DSPIC33FJ128MC202-E/MM Datasheet - Page 2
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DSPIC33FJ128MC202-E/MM
Manufacturer Part Number
DSPIC33FJ128MC202-E/MM
Description
16-bit DSC, 128KB Flash,Motor,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128MC202-E/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128MC202-E/MM
Manufacturer:
Microchip Technology
Quantity:
135
TABLE 1:
TABLE 2:
DS80442F-page 2
dsPIC33FJ128MC202
dsPIC33FJ128MC204
dsPIC33FJ128MC802
dsPIC33FJ128MC804
Note 1:
Note 1:
Module
UART
UART
UART
I
SPI
2
SPI
I
I
I
I
I
C™
2
2
2
2
2
2:
C
C
C
C
C
The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on
Device and Revision IDs for your specific device.
Only those issues indicated in the last column apply to the current silicon revision.
Part Number
Frame Mode
SILICON DEVREV VALUES (CONTINUED)
SILICON ISSUE SUMMARY
High-Speed
SFR Writes
Addressing
Addressing
Addressing
Operation
Interrupts
Transmit
IR Mode
Feature
Mode
10-bit
10-bit
10-bit
—
—
Number
Item
10.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
The 16x baud clock signal on the BCLK pin is present
only when the module is transmitting.
When the UART is in 4x mode (BRGH = 1) and using
two Stop bits (STSEL = 1), it may sample the first Stop
bit instead of the second one.
The SPI Transmit Buffer Full (SPITBF) flag does not get
set immediately after writing to the buffer.
The SPI module will generate incorrect frame
synchronization pulses in Frame Master mode if
FRMDLY = 1.
The BCL bit in I2CSTAT can only be cleared with Word
instructions, and can be corrupted with byte instructions
and bit operations.
When the I
using the same address bits (A10 and A9) as other I
devices, A10 and A9 bits may not work as expected.
When the I
an address of 0x102, the I2CxRCV register content for
the lower address byte is 0x01 rather than 0x02.
With the I
external Interrupt Input functions (if any) associated with
SCL and SDA pins will not reflect the actual digital logic
levels on the pins.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register, on address match if the Least
Significant bits (LSbs) of the address are the same as
the 7-bit reserved addresses.
After the ACKSTAT bit is set when receiving a NACK, it
may be cleared by the reception of a Start or Stop bit.
The UART error interrupt may not occur, or may occur at
an incorrect time, if multiple errors occur during a short
period of time.
2
C module enabled, the PORT bits and
2
2
Device ID
C module is configured as a 10-bit slave with
C module is configured for 10-bit addressing
0x062B
0x0621
0x0623
0x0629
Issue Summary
(1)
0x3001
Revision ID for Silicon Revision
A1
© 2010 Microchip Technology Inc.
0x3002
A2
2
C
0x3002
A1 A2 A3 A4
X
X
X
X
X
X
X
X
X
X
X
A3
Revisions
Affected
X
X
X
X
X
X
X
X
X
X
X
0x3003
X
X
X
X
X
X
X
X
X
X
X
A4
(1)
(2)
X
X
X
X
X
X
X
X
X
X
X