DSPIC33FJ128MC202-E/MM Microchip Technology, DSPIC33FJ128MC202-E/MM Datasheet - Page 6
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DSPIC33FJ128MC202-E/MM
Manufacturer Part Number
DSPIC33FJ128MC202-E/MM
Description
16-bit DSC, 128KB Flash,Motor,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128MC202-E/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128MC202-E/MM
Manufacturer:
Microchip Technology
Quantity:
135
12. Module: UART
13. Module: Comparator
14. Module: Internal Voltage Regulator
DS80442F-page 6
When the UART is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
If CMCON<CxOUTEN> bit is set and the
comparator
disabled, the remappable comparator output pins,
C1OUT and C2OUT, cannot be used as general
purpose I/O pins.
Work around
When the comparator module is disabled the
CMCON<CxOUTEN> bit should be reset so that
the remappable comparator output pins C1OUT
and C2OUT are not driven onto the output pad.
Affected Silicon Revisions
When the VREGS bit (RCON<8>) is set to a logic
‘0’, the device may reset and a higher Sleep
current may be observed.
Work around
Ensure VREGS bit (RCON<8>) is set to a logic ‘1’
for device Sleep mode operation.
Affected Silicon Revisions
A1
A1
A1
X
X
X
A2
A2
A2
X
X
X
module
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
CMCON<CxEN>
bit
is
15. Module: PSV Operations
16. Module: ECAN
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (Word or Byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
Affected Silicon Revisions
The WAKIF bit in the CxINTF register cannot be
cleared by software instruction after the device is
interrupted from Sleep due to activity on the CAN
bus.
When the device wakes up from Sleep due to CAN
bus activity, the ECAN module is placed in
operational mode. The ECAN Event interrupt
occurs due to the WAKIF flag. Trying to clear the
flag in the Interrupt Service Routine (ISR) may not
clear the flag. The WAKIF bit being set will not
cause
execution.
Work around
Although the WAKIF bit does not clear, the device
Sleep and ECAN Wake function continue to work
as expected. If the ECAN event is enabled, the
CPU will enter the Interrupt Service Routine due to
the WAKIF flag getting set. The application can
maintain a secondary flag, which tracks the device
Sleep and Wake events.
Affected Silicon Revisions
A1
A1
mode) with pre/post-decrement
X
X
A2
A2
X
X
repetitive
A3
A3
X
X
© 2010 Microchip Technology Inc.
A4
A4
Interrupt
X
X
Service
Routine