DSPIC33FJ128MC802T-I/MM Microchip Technology, DSPIC33FJ128MC802T-I/MM Datasheet - Page 238
![16-bit DSC, 128KB Flash,Motor,CAN,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm T/R](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC33FJ128MC802T-I/MM
Manufacturer Part Number
DSPIC33FJ128MC802T-I/MM
Description
16-bit DSC, 128KB Flash,Motor,CAN,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128MC802T-I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ128MC802T-I/MMTR
- Current page: 238 of 436
- Download datasheet (6Mb)
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
REGISTER 19-2:
DS70291E-page 238
bit 3
bit 2
bit 1
bit 0
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R_W: Read/Write Information bit (when operating as I
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware set or clear after reception of I
RBF: Receive Buffer Full Status bit
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
2
C device address byte.
2
C slave)
© 2011 Microchip Technology Inc.
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