DSPIC33FJ128MC802T-I/MM Microchip Technology, DSPIC33FJ128MC802T-I/MM Datasheet - Page 91
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DSPIC33FJ128MC802T-I/MM
Manufacturer Part Number
DSPIC33FJ128MC802T-I/MM
Description
16-bit DSC, 128KB Flash,Motor,CAN,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128MC802T-I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ128MC802T-I/MMTR
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7.0
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04
controller reduces the numerous peripheral interrupt
request signals to a single interrupt request signal to
the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 CPU.
The interrupt controller has the following features:
• Up to eight processor exceptions and software
• Eight user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
• Fixed interrupt entry and return latencies
7.1
The Interrupt Vector Table (IVT), shown in
resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
eight nonmaskable trap vectors plus up to 118 sources
of interrupt. In general, each interrupt source has its
own vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
traps
source
support
Note 1: This data sheet summarizes the features
and
2: Some registers and associated bits
INTERRUPT CONTROLLER
Interrupt Vector Table
of
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 32. Interrupts (Part
III)”
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
dsPIC33FJ128MCX02/X04
(DS70214)
the
dsPIC33FJ32MC302/304,
of
the
“dsPIC33F/
family
Figure
interrupt
and
7-1,
of
in
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 takes priority over interrupts at any other
vector address.
dsPIC33FJ32MC302/304,
and dsPIC33FJ128MCX02/X04 devices implement up
to 53 unique interrupts and five nonmaskable traps.
These are summarized in
7.1.1
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in
AIVT
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a means to
switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
7.2
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 device clears its
registers in response to a Reset, which forces the PC
to zero. The digital signal controller then begins
program execution at location 0x000000. A GOTO
instruction at the Reset address can redirect program
execution to the appropriate start-up routine.
Note:
is
Reset Sequence
provided
ALTERNATE INTERRUPT VECTOR
TABLE
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
by
Table
the
Figure
dsPIC33FJ64MCX02/X04
7-1.
ALTIVT
7-1. Access to the
DS70291E-page 91
control
bit
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