DSPIC33FJ16GS502-E/MM Microchip Technology, DSPIC33FJ16GS502-E/MM Datasheet - Page 145
![16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 28 QFN-S 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC33FJ16GS502-E/MM
Manufacturer Part Number
DSPIC33FJ16GS502-E/MM
Description
16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ06GS101-ISO.pdf
(346 pages)
2.DSPIC33FJ06GS101-ISO.pdf
(18 pages)
3.DSPIC33FJ06GS101-ISO.pdf
(16 pages)
Specifications of DSPIC33FJ16GS502-E/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ16GS502-E/MM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- DSPIC33FJ06GS101-ISO PDF datasheet
- DSPIC33FJ06GS101-ISO PDF datasheet #2
- DSPIC33FJ06GS101-ISO PDF datasheet #3
- Current page: 145 of 346
- Download datasheet (6Mb)
REGISTER 8-5:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10-8
bit 7
bit 6
bit 5-0
ASRCSEL
ENAPLL
R/W-0
R/W-0
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
ENAPLL: Auxiliary PLL Enable bit
1 = APLL is enabled
0 = APLL is disabled
APLLCK: APLL Locked Status bit (read-only)
1 = Indicates that auxiliary PLL is in lock
0 = Indicates that auxiliary PLL is not in lock
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1 = Auxiliary Oscillators provides the source clock for auxiliary clock divider
0 = Primary PLL (F
Unimplemented: Read as ‘0’
APSTSCLR<2:0>: Auxiliary Clock Output Divider bits
111 = Divided by 1
110 = Divided by 2
101 = Divided by 4
100 = Divided by 8
011 = Divided by 16
010 = Divided by 32
001 = Divided by 64
000 = Divided by 256
ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit
1 = Primary oscillator is the clock source
0 = No clock input is selected
FRCSEL: Select Reference Clock Source for Auxiliary PLL bit
1 = Select FRC clock for auxiliary PLL
0 = Input clock source is determined by ASRCSEL bit setting
Unimplemented: Read as ‘0’
FRCSEL
APLLCK
R/W-0
R-0
ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
SELACLK
R/W-0
VCO
U-0
—
) provides the source clock for auxiliary clock divider
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
R/W-0
U-0
—
APSTSCLR<2:0>
x = Bit is unknown
R/W-0
U-0
—
DS70318D-page 143
R/W-0
bit 0
U-0
—
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