DSPIC33FJ16GS502-E/MM Microchip Technology, DSPIC33FJ16GS502-E/MM Datasheet - Page 263
![16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 28 QFN-S 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC33FJ16GS502-E/MM
Manufacturer Part Number
DSPIC33FJ16GS502-E/MM
Description
16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ06GS101-ISO.pdf
(346 pages)
2.DSPIC33FJ06GS101-ISO.pdf
(18 pages)
3.DSPIC33FJ06GS101-ISO.pdf
(16 pages)
Specifications of DSPIC33FJ16GS502-E/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ16GS502-E/MM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- DSPIC33FJ06GS101-ISO PDF datasheet
- DSPIC33FJ06GS101-ISO PDF datasheet #2
- DSPIC33FJ06GS101-ISO PDF datasheet #3
- Current page: 263 of 346
- Download datasheet (6Mb)
REGISTER 20-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-9
bit 8
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: DACOUT can be associated only with a single comparator at any given time. The software must ensure
CMPON
R/W-0
R/W-0
INSEL<1:0>
that multiple comparators do not enable the DAC output by setting their respective DACOE bit.
CMPON: Comparator Operating Mode bit
1 = Comparator module is enabled
0 = Comparator module is disabled (reduces power consumption)
Unimplemented: Read as ‘0’
CMPSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode.
0 = Continue module operation in Idle mode
If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables ALL comparators while in
Idle mode.
Reserved: Read as ‘0’
DACOE: DAC Output Enable
1 = DAC analog voltage is output to DACOUT pin
0 = DAC analog voltage is not connected to DACOUT pin
INSEL<1:0>: Input Source Select for Comparator bits
00 = Select CMPxA input pin
01 = Select CMPxB input pin
10 = Select CMPxC input pin
11 = Select CMPxD input pin
EXTREF: Enable External Reference bit
1 = External source provides reference to DAC (maximum DAC voltage determined by external
0 = Internal reference sources provide reference to DAC (maximum DAC voltage determined by
Reserved: Read as ‘0’
CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit
Reserved: Read as ‘0’
CMPPOL: Comparator Output Polarity Control bit
1 = Output is inverted
0 = Output is non-inverted
RANGE: Selects DAC Output Voltage Range bit
1 = High Range: Max DAC Value = AV
0 = Low Range: Max DAC Value = INTREF, 1.2V, ±1%
R/W-0
voltage source)
RANGE bit setting)
U-0
—
CMPCONx: COMPARATOR CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
CMPSIDL
EXTREF
R/W-0
R/W-0
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
U-0
U-0
Preliminary
—
—
DD
/2, 1.65V at 3.3V AV
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CMPSTAT
R/W-0
U-0
—
(1)
DD
U-0
U-0
—
—
x = Bit is unknown
CMPPOL
R/W-0
U-0
—
DS70318D-page 261
DACOE
RANGE
R/W-0
R/W-0
bit 8
bit 0
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