DSPIC33FJ16GS502-E/SP Microchip Technology, DSPIC33FJ16GS502-E/SP Datasheet - Page 11

• Manufacturer Part Number: DSPIC33FJ16GS502-E/SP
• Description: 16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-E/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

29. Module: Analog Comparator
30. Module: Auxiliary PLL
EXAMPLE 2:
© 2010 Microchip Technology Inc.
AD1CON1bits.ADON = 0;
__asm__ volatile ("REPEAT #50");
__asm__ volatile ("NOP");
Sleep();
The
(INTREF) for the Analog Comparator provides the
reference to the Analog Comparator if the
EXTREF bit (CMPCONx<5>) = 0 and the RANGE
bit (CMPCONx<0>) = 0.
The data sheet states that the INTREF voltage
should be 1.2V nominal and within +/- 1%.
However, the Internal Bandgap Reference Voltage
does not meet the accuracy specification as stated
in the data sheet. The actual range of voltages for
the internal bandgap is 1.25V to 1.41V.
Work arounds
To avoid this issue, implement one of the following
two work arounds, depending on the application
requirements.
Work around 1:
Use an external voltage reference for the Analog
Comparator
(CMPCONx<5>) = 1 and providing an external
reference to the EXTREF pin.
Work around 2:
Use the high-range setting for the internal
reference
(CMPCONx<5>) = 0 and the RANGE bit
(CMPCONx<0>) = 1. This setting uses AV
the comparator reference voltage.
Affected Silicon Revisions
For extended temperature devices (designated
with the -E suffix in the device part number) with
the date code of 09XX, the Auxiliary PLL input
frequency
specification range at operating temperatures
above 85ºC.
A2
X
Internal
A3
X
does
by
A4
by
X
Bandgap
setting
setting
not
meet
the
Reference
the
the
EXTREF
EXTREF
//Disable the ADC module
//Wait 50 Tcy
//Repeat NOP 51 times
// Execute PWRSAV #0 and go to Sleep
published
Voltage
DD
/2 as
bit
bit
31. Module: ADC
Note:
Note:
Work around
Use the internal FRC oscillator as the input to the
Auxiliary PLL, or use the external oscillator with a
frequency of 7.37 MHz.
Affected Silicon Revisions
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work arounds
Work around 1:
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV
instruction.
Work around 2:
If the ADC module was previously initialized and
enabled, before entering Sleep, execute the lines
of code provided in
Affected Silicon Revisions
A2
A2
X
X
The ADC module must be reinitialized by
the user application before resuming ADC
operation.
Unlike
application does not need to reinitialize
the ADC module; however, it is necessary
to re-enable the ADC module by setting
the ADON bit after waking from Sleep.
A3
A3
X
X
PD
) may exceed the specifications listed
A4
A4
X
X
Work
Example
around
2.
DS80439H-page 11
PD
1,
specifications
the
user
#0