DSPIC33FJ256GP510A-I/PT Microchip Technology, DSPIC33FJ256GP510A-I/PT Datasheet - Page 82

• Manufacturer Part Number: DSPIC33FJ256GP510A-I/PT
• Description: 16 Bit MCU/DSP 40MIPS 256KB FLASH 100 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256GP510A-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Package: 100TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 85
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 32-chx10-bit|32-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJXXXGPX06A/X08A/X10A
5.2
The dsPIC33FJXXXGPX06A/X08A/X10A Flash pro-
gram memory array is organized into rows of 64
instructions or 192 bytes. RTSP allows the user to
erase a page of memory, which consists of eight rows
(512 instructions) at a time, and to program one row or
one word at a time.
and programming times. The 8-row erase pages and
single row write rows are edge-aligned, from the begin-
ning of program memory, on boundaries of 1536 bytes
and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers in sequential order. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written.
programming each row.
5.3
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode.
programming operation is finished.
The programming time depends on the FRC accuracy
(see
Tuning register (see
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see
EQUATION 5-1:
DS70593C-page 82
--------------------------------------------------------------------------------------------------------------------------- -
7.37 MHz
Table
The
RTSP Operation
Programming Operations
A
25-19) and the value of the FRC Oscillator
×
programming
processor
(
FRC Accuracy
Table 25-12
Register
PROGRAMMING TIME
T
stalls
cycle
)%
9-4). Use the following
illustrates typical erase
×
Table
(waits)
(
FRC Tuning
is
25-12).
required
until
)%
the
for
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
Register
write time is equal to
EQUATION 5-2:
The maximum row write time is equal to
EQUATION 5-3:
Setting the WR bit (NVMCON<15>) starts the
operation, and the WR bit is automatically cleared
when the operation is finished.
5.4
The two SFRs that are used to read and write the
program Flash memory are:
•
•
The NVMCON register
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY
used for write protection. To start a programming or
erase sequence, the user must consecutively write 0x55
and 0xAA to the NVMKEY register. Refer to
“Programming Operations”
T
T
RW
RW
NVMCON: Flash Memory Control Register
NVMKEY: Non-Volatile Memory Key Register
=
=
----------------------------------------------------------------------------------------------- - 1.586ms
7.37 MHz
----------------------------------------------------------------------------------------------- - 1.435ms
7.37 MHz
9-4) are set to ‘b111111, the minimum row
Control Registers
(Register
×
×
(
(
11064 Cycles
11064 Cycles
5-2) is a write-only register that is
1 0.05
1
Equation
–
+
MINIMUM ROW WRITE
TIME
MAXIMUM ROW WRITE
TIME
© 2011 Microchip Technology Inc.
0.05
(Register
)
)
×
×
for further details.
5-2.
(
(
1 0.00375
1 0.00375
–
–
5-1) controls which
Equation
Section 5.3
)
)
=
=
5-3.