DSPIC33FJ64MC202-E/SP Microchip Technology, DSPIC33FJ64MC202-E/SP Datasheet - Page 239
![16-bit DSC, 64KB Flash,Motor, DMA,40 MIPS,nanoWatt 28 SPDIP .300in TUBE](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ64MC202-E/SP
Manufacturer Part Number
DSPIC33FJ64MC202-E/SP
Description
16-bit DSC, 64KB Flash,Motor, DMA,40 MIPS,nanoWatt 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC202-E/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REGISTER 19-3:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9-0
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
AMSK7
R/W-0
U-0
—
Unimplemented: Read as ‘0’
AMSKx: Mask for Address bit x Select bit
1 = Enable masking for bit x of incoming message address; bit match not required in this position
0 = Disable masking for bit x; bit match required in this position
AMSK6
R/W-0
U-0
—
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
W = Writable bit
‘1’ = Bit is set
AMSK5
R/W-0
U-0
—
AMSK4
R/W-0
U-0
—
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
AMSK3
R/W-0
U-0
—
AMSK2
R/W-0
U-0
—
x = Bit is unknown
AMSK9
AMSK1
R/W-0
R/W-0
DS70291E-page 239
AMSK8
AMSK0
R/W-0
R/W-0
bit 8
bit 0
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