DSPIC33FJ64MC202-E/SP Microchip Technology, DSPIC33FJ64MC202-E/SP Datasheet - Page 54
![16-bit DSC, 64KB Flash,Motor, DMA,40 MIPS,nanoWatt 28 SPDIP .300in TUBE](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ64MC202-E/SP
Manufacturer Part Number
DSPIC33FJ64MC202-E/SP
Description
16-bit DSC, 64KB Flash,Motor, DMA,40 MIPS,nanoWatt 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC202-E/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TABLE 4-15:
TABLE 4-16:
TABLE 4-17:
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
Legend:
ADC1BUF0
AD1CON1
AD1CON2
AD1CON3
AD1CHS123
AD1CHS0
AD1PCFGL
AD1CSSL
AD1CON4
Legend:
SFR Name
SFR Name
SPI2CON1
SPI2CON2
SPI2STAT
File Name
SPI2BUF
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
0240
0242
0244
0248
Addr
0260
0262
0264
0268
032C
SFR
SFR
Addr
0300
0320
0322
0324
0326
0328
0330
0332
SPI1 REGISTER MAP
SPI2 REGISTER MAP
ADC1 REGISTER MAP FOR dsPIC33FJ64MC202/802, dsPIC33FJ128MC202/802 AND dsPIC33FJ32MC302
FRMEN
FRMEN
CH0NB
SPIEN
SPIEN
ADON
Bit 15
Bit 15
ADRC
Bit 15
—
—
—
—
—
—
VCFG<2:0>
Bit 14
SPIFSD
SPIFSD
—
—
—
—
—
—
—
Bit 14
Bit 14
—
—
—
—
ADSIDL ADDMABM
Bit 13
—
—
—
—
—
—
FRMPOL
FRMPOL
SPISIDL
SPISIDL
Bit 13
Bit 13
—
—
Bit 12
—
—
—
—
—
DISSCK
DISSCK
Bit 12
Bit 12
—
—
—
—
Bit 11
DISSDO MODE16
DISSDO MODE16
—
—
—
—
—
—
Bit 11
Bit 11
—
—
—
—
CH0SB<4:0>
SAMC<4:0>
CSCNA
AD12B
Bit 10
CH123NB<1:0>
—
—
—
Bit 10
Bit 10
—
—
—
—
SPI1 Transmit and Receive Buffer Register
SPI2 Transmit and Receive Buffer Register
Bit 9
—
—
—
FORM<1:0>
CHPS<1:0>
Bit 9
SMP
Bit 9
SMP
—
—
—
—
CH123SB
Bit 8
ADC Data Buffer 0
—
—
—
Bit 8
CKE
Bit 8
CKE
—
—
—
—
CH0NA
BUFS
Bit 7
—
—
—
—
SSEN
SSEN
Bit 7
Bit 7
—
—
—
—
SSRC<2:0>
SPIROV
SPIROV
Bit 6
Bit 6
CKP
Bit 6
CKP
—
—
—
—
—
—
—
—
PCFG5
CSS5
MSTEN
MSTEN
Bit 5
Bit 5
Bit 5
—
—
—
—
—
—
—
PCFG4
CSS4
Bit 4
Bit 4
Bit 4
—
—
—
—
—
—
—
ADCS<7:0>
SMPI<3:0>
SPRE<2:0>
SPRE<2:0>
SIMSAM
PCFG3
CSS3
Bit 3
Bit 3
Bit 3
—
—
—
—
—
—
CH0SA<4:0>
PCFG2
ASAM
CSS2
Bit 2
Bit 2
Bit 2
CH123NA<1:0>
—
—
—
—
DMABL<2:0>
FRMDLY
FRMDLY
SPITBF
SPITBF
PCFG1
SAMP
BUFM
CSS1
Bit 1
Bit 1
Bit 1
PPRE<1:0>
PPRE<1:0>
CH123SA
SPIRBF
SPIRBF
PCFG0
DONE
CSS0
ALTS
Bit 0
Bit 0
Bit 0
—
—
Resets
Resets
Resets
0000
0000
0000
0000
0000
0000
0000
0000
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
All
All
All
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