EP20K400CB652C7 Altera, EP20K400CB652C7 Datasheet - Page 10

• Manufacturer Part Number: EP20K400CB652C7
• Description: APEX 20KC
• Manufacturer: Altera

APEX 20KC Programmable Logic Device Data Sheet
Figure 3. LAB Structure
10
LEs drive local,
MegaLAB, row,
and column
interconnects.
MegaLAB Interconnect
To/From
Adjacent LAB,
ESB, or IOEs
Local Interconnect
Row
Interconnect
Each LAB contains dedicated logic for driving control signals to its LEs
and ESBs. The control signals include clock, clock enable, asynchronous
clear, asynchronous preset, asynchronous load, synchronous clear, and
synchronous load signals. A maximum of six control signals can be used
at a time. Although synchronous load and clear signals are generally used
when implementing counters, they can also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked (e.g., any LE in a particular LAB
using CLK1 will also use CLKENA1). LEs with the same clock but different
clock enable signals either use both clock signals in one LAB or are placed
into separate LABs.
If both the rising and falling edges of a clock are used in a LAB, both LAB-
wide clock signals are used.
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
Column
Interconnect
Altera Corporation
To/From
Adjacent LAB,
ESB, or IOEs