EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 125
EP3C16F484A7N
Manufacturer Part Number
EP3C16F484A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C16F484A7N.pdf
(274 pages)
Specifications of EP3C16F484A7N
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / Rohs Status
Compliant
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High-Speed I/O Interface
© December 2009
CIII51008-3.2
f
Altera Corporation
This chapter describes the high-speed differential I/O features and resources in the
Cyclone III device family.
High-speed differential I/O standards have become popular in high-speed interfaces
because of their significant advantages over single-ended I/O standards. The Altera
Cyclone
BLVDS, reduced swing differential signaling (RSDS), mini-LVDS, and point-to-point
differential signaling (PPDS).
This chapter contains the following sections:
■
■
■
■
■
■
Cyclone III device family I/Os are separated into eight I/O banks, as shown in
Figure
LVDS, RSDS, mini-LVDS, and PPDS are on the left and right I/O banks. These I/O
standards are also supported on the top and bottom I/O banks using external
resistors. On the left and right I/O banks, some of the differential pin pairs (p and n
pins) of the true output drivers are not located on adjacent pins. In these cases, a
power pin is located between the p and n pins. These I/O standards are also
supported on all I/O banks using two single-ended output with the second output
programmed as inverted, and an external resistor network. True input buffers for
these I/O standards are supported on all I/O banks.
For more information about the location of Cyclone III device family true differential
pins, refer to the
“High-Speed I/O Interface” on page 7–1
“High-Speed I/O Standards Support” on page 7–7
“True Output Buffer Feature” on page 7–15
“High-Speed I/O Timing” on page 7–16
“Design Guidelines” on page 7–17
“Software Overview” on page 7–18
7–1. Each bank has an independent power supply. True output drivers for
®
III device family (Cyclone III and Cyclone III LS devices) supports LVDS,
Cyclone III Devices Pin-Outs
7. High-Speed Differential Interfaces in
the Cyclone III Device Family
on the Altera website.
Cyclone III Device Handbook, Volume 1
®
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