EP3C16F484A7N Altera, EP3C16F484A7N Datasheet - Page 192

• Manufacturer Part Number: EP3C16F484A7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C16F484A7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Compliant

9–32
Cyclone III Device Handbook, Volume 1
Figure 9–12
interfaces to minimize signal integrity issue.
Figure 9–12. Balanced Star Routing
Notes to
(1) Altera does not recommend M to exceed six inches as listed in
(2) Altera recommends using a balanced star routing. Try to keep the N length equal and as short as possible to minimize
Estimating the AP Configuration Time
AP configuration time is dominated by the time it takes to transfer data from the
parallel flash to the Cyclone III devices. This parallel interface is clocked by the
Cyclone III DCLK output (generated from an internal oscillator). As listed in
on page
20 MHz (50 ns). In word-wide cascade programming, the DATA[15..0] bus transfers
a 16-bit word and essentially cuts configuration time to approximately 1/16 of the AS
configuration time. Therefore, the maximum configuration time estimation for an
EP3C40 device (9,600,000 bits of uncompressed data) is defined in
Equation
Equation 9–4.
Equation 9–5.
To estimate a typical configuration time, use the typical DCLK period listed in
Table 9–8 on page
configuration time is 20 ms.
RBF Size
9,600,000 bits
reflection noise from the transmission line. The M length is applicable for this setup.
Figure
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
×
9–13, the DCLK minimum frequency when using the 40-MHz oscillator is
9–5.
⎛
⎝
maximum DCLK period
- ----------------------------------------------------- -
16 bits per DCLK cycle
shows the recommended balanced star routing for multiple bus master
9–12:
×
⎛
⎝
--------------- -
16 bits
50 ns
9–13. With a typical DCLK period of 33.33 ns, the typical
⎞
⎠
Master Device
Cyclone III
=
30 ms
DCLK
⎞
⎠
=
estimated maximum configuration time
M (1)
Table 9–12 on page
Numonyx Flash
Master Device
External
© December 2009 Altera Corporation
N (2)
N (2)
9–30.
Equation 9–4
Configuration Features
Table 9–8
and