EPM1270GT144I5N Altera, EPM1270GT144I5N Datasheet
EPM1270GT144I5N
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EPM1270GT144I5N Summary of contents
Page 1
... Revision History Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. © August 2009 Altera Corporation Section I. MAX II Device Family Data Sheet II devices. ...
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... I–2 MAX II Device Handbook Section I: MAX II Device Family Data Sheet Revision History © August 2009 Altera Corporation ...
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... Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz Supports hot-socketing ■ Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry ■ compliant with IEEE Std. 1149.1-1990 ■ ISP circuitry compliant with IEEE Std. 1532 © August 2009 Altera Corporation 1. Introduction MAX II Device Handbook ...
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... MAX II Logic Element to DC and Switching –6 –7 –8 — — — — — — — — — — — — © August 2009 Altera Corporation ...
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... Micro FineLine FineLine Package BGA BGA Pitch (mm) 0.5 0.5 Area (mm2 Length × width 5 × × 6 (mm × mm) © August 2009 Altera Corporation II software can automatically cross-reference ® 144-Pin 100-Pin Micro FineLine 100-Pin 144-Pin FineLine BGA TQFP TQFP BGA 80 80 — ...
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... Updated document with MAX IIZ information. Chapter 1: Introduction Referenced Documents EPM240G EPM570G EPM1270G EPM2210G EPM240Z EPM570Z (1) 1.8 V 1.5 V, 1.8 V, 2.5 V, 3.3 V external supply powers the device core directly. white paper Summary of Changes — — — — © August 2009 Altera Corporation ...
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... Updated timing numbers in Table 1-1. ■ version 1.3 December 2004, Updated timing numbers in Table 1-1. ■ version 1.2 June 2004, Updated timing numbers in Table 1-1. ■ version 1.1 © August 2009 Altera Corporation Changes Made 1–5 Summary of Changes — — — MAX II Device Handbook ...
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... MAX II Device Handbook Chapter 1: Introduction Document Revision History © August 2009 Altera Corporation ...
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... The global clock lines can also be used for control signals such as clear, preset, or output enable. © October 2008 Altera Corporation 2. MAX II Architecture MAX II Device Handbook ...
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... IOE Logic Logic Element Element Logic Logic Element Element Logic Logic Element Element Logic Logic Element Element MultiTrack Interconnect chapter in the MAX II Device Handbook. Chapter 2: MAX II Architecture Functional Description IOE Logic Array BLock (LAB) Hot Socketing © October 2008 Altera Corporation ...
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... The device shown is an EPM570 device. EPM1270 and EPM2210 devices have a similar floorplan with more LABs. For EPM240 devices, the CFM and UFM blocks are located on the left side of the device. © October 2008 Altera Corporation LAB Rows Short LAB Rows ...
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... LE6 LE7 LE8 LE9 LAB Local Interconnect Figure 2–4 shows the DirectLink connection. Chapter 2: MAX II Architecture Logic Array Blocks Column Interconnect Fast I/O connection to IOE (1) DirectLink interconnect from adjacent LAB or IOE DirectLink interconnect to adjacent LAB or IOE © October 2008 Altera Corporation ...
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... LAB-wide control signals. The MultiTrack interconnect structure drives the LAB local interconnect for non-global control signal generation. The MultiTrack interconnect’s inherent low skew allows clock and control signal distribution in addition to data. circuit. © October 2008 Altera Corporation LE0 LE1 LE2 LE3 ...
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... LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and DirectLink interconnects. See Figure 2–6. MAX II Device Handbook labclkena2 labclkena1 syncload labclk2 asyncload or labpre Chapter 2: MAX II Architecture Logic Elements labclr2 addnsub labclr1 synclr © October 2008 Altera Corporation ...
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... LUT of the same LE so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output. © October 2008 Altera Corporation Register chain routing from previous LE ...
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... MAX II Device Handbook for more information about LUT chain and register chain © October 2008 Altera Corporation Chapter 2: MAX II Architecture Logic Elements “MultiTrack ...
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... For example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry in0 or data1 + data2 + carry-in1 © October 2008 Altera Corporation Figure 2–7). The Quartus II Compiler automatically sload sclear (LAB Wide) ...
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... Wide) aclr (LAB Wide) Register Feedback Carry-Out1 Chapter 2: MAX II Architecture Logic Elements aload Row, column, and Q direct link routing Row, column, and direct link routing CLRN Local routing LUT chain connection Register chain output © October 2008 Altera Corporation ...
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... Sum5 A5 LE4 Sum6 A6 LE5 B6 Sum7 A7 LE6 B7 Sum8 A8 LE7 B8 Sum9 A9 LE8 B9 Sum10 A10 LE9 B10 LAB Carry-Out © October 2008 Altera Corporation LAB Carry-In Carry-In0 Carry-In1 data1 data2 Carry-Out0 To top of adjacent LAB 2–11 LUT Sum LUT LUT LUT Carry-Out1 MAX II Device Handbook ...
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... The DirectLink interconnect allows an LAB to drive into the local interconnect of its left and right neighbors. The DirectLink interconnect provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. MAX II Device Handbook Chapter 2: MAX II Architecture MultiTrack Interconnect © October 2008 Altera Corporation ...
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... The LUT chain connection allows the combinational output directly drive the fast input of the LE right below it, bypassing the local interconnect. These resources can be used as a high-speed connection for wide fan-in © October 2008 Altera Corporation Adjacent LAB can drive onto another C4 Column Interconnects (1) LAB’ ...
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... LAB LE0 LUT Chain Register Chain Routing to Routing to Adjacent Adjacent LE LE's Register Input LE1 Local LE2 Interconnect LE3 LE4 LE5 LE6 LE7 LE8 LE9 Chapter 2: MAX II Architecture MultiTrack Interconnect Figure 2–11 Figure 2–12 shows the C4 © October 2008 Altera Corporation ...
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... Figure 2–12. C4 Interconnect Connections Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Note to Figure 2–12: (1) Each C4 interconnect can drive either up or down four rows. © October 2008 Altera Corporation (Note 1) Local Interconnect 2–15 C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect ...
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... Figure 2–13 shows © October 2008 Altera Corporation ...
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... LAB clock signals and one LAB clear signal. Other control signal types route from the global clock network into the LAB local interconnect. See “LAB Control Signals” on page 2–5 © October 2008 Altera Corporation GCLK0 GCLK1 GCLK2 ...
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... Program, erase, and busy signals MAX II Device Handbook UFM Block (2) CFM Block shows the UFM block and interface signals. The logic array is Chapter 2: MAX II Architecture User Flash Memory Block LAB Column clock[3..0] 4 I/O Block Region © October 2008 Altera Corporation ...
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... UFM block). Since sector erase is required before a program or write, having two sectors enables a sector size of data to be left untouched while the other sector is erased and programmed with new data. © October 2008 Altera Corporation UFM Block Program ...
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... MAX II Device Handbook. Using User Flash Memory in MAX II Devices and Figure 2–2. The UFM block for the EPM240 device is Chapter 2: MAX II Architecture User Flash Memory Block chapter in Figure 2–16. The interface regions Figure 2–17. © October 2008 Altera Corporation ...
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... Figure 2–16. EPM240 UFM Block LAB Row Interface Note to Figure 2–16: (1) The UFM block inputs and outputs can drive to/from all types of interconnects, not only DirectLink interconnects from adjacent row LABs. © October 2008 Altera Corporation (Note 1) CFM Block UFM Block LAB ...
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... CCINT Figure Voltage 1.8-V on Regulator VCCINT Pins Voltage MAX II Device Chapter 2: MAX II Architecture MultiVolt Core LAB LAB LAB supply. An internal linear voltage 2–18. The voltage regulator is not external CC 1.8-V Core Voltage MAX IIG or MAX IIZ Device © October 2008 Altera Corporation ...
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... A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O block provides faster output delays for clock-to-output and t This connection exists for data output signals, not output enable signals or input signals. Figure © October 2008 Altera Corporation 2–20, Figure 2–21, and Figure 2–22 2– ...
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... MAX II Device Handbook DEV_OE Optional PCI Clamp ( CCIO CCIO Drive Strength Control Open-Drain Output Slew Control Optional Schmitt Programmable Trigger Input Input Delay Chapter 2: MAX II Architecture I/O Structure Programmable Pull-Up I/O Pin Optional Bus-Hold Circuit © October 2008 Altera Corporation ...
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... Adjacent LAB LAB Local Interconnect Note to Figure 2–20: (1) Each of the seven IOEs in the row I/O block can have one data_out or fast_out output, one OE output, and one data_in input. © October 2008 Altera Corporation (Note 1) C4 Interconnects I/O Block Local Interconnect data_out [6..0] ...
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... Column I/O Block OE fast_out [3..0] [3.. Fast I/O Interconnect LAB Column Path Clock [3..0] LAB LAB LAB Local Interconnect Chapter 2: MAX II Architecture I/O Structure Column I/O Block Contains IOEs data_in [3..0] 4 LAB LAB Local Interconnect C4 Interconnects © October 2008 Altera Corporation ...
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... PCI drive compliance on outputs. You must use Bank 3 for designs requiring PCI compliant I/O pins. The Quartus II software automatically places I/O pins in this bank if assigned with the PCI I/O standard. © October 2008 Altera Corporation Output Supply Voltage Type ...
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... For example, when CCIO except for PCI. These pins reside in Bank 1 for all MAX II Chapter 2: MAX II Architecture I/O Structure Also Supports the 3.3-V PCI I/O Standard I/O Bank 3 powers both CCIO setting for Bank 1. CCIO © October 2008 Altera Corporation ...
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... The Quartus II software uses the maximum current strength as the default setting. The PCI I/O standard is always set with no alternate setting. © October 2008 Altera Corporation 33-MHz PCI All Speed Grades –3 Speed Grade All Speed Grades – ...
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... IOH/IOL Current Strength Setting (mA) current strength numbers shown are for a condition maximum is specified by the I/O standard. For 2.5-V LVTTL/LVCMOS, the 1.7 V and the I condition 0.7 V. OUT OL OUT Chapter 2: MAX II Architecture I/O Structure minimum, where the V minimum OUT OUT OL OH © October 2008 Altera Corporation ...
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... I/O banks available in the devices where each set of VCC pins powers one I/O bank. The EPM240 and EPM570 devices have two I/O banks respectively while the EPM1270 and EPM2210 devices have four I/O banks respectively. © October 2008 Altera Corporation to prevent overdriving signals. If the bus-hold feature is enabled, CCIO ...
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... MAX II Device Handbook chapter in the MAX II Device Handbook Chapter 2: MAX II Architecture Referenced Documents Output Signal 1.8 V 2.5 V 3.3 V 5.0 V — — — — v — — — (3) — — (6) (6) (7) AN chapter in the MAX II Device © October 2008 Altera Corporation ...
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... December 2004, Added a paragraph to page 2-15. ■ version 1.2 June 2004, Added CFM acronym. Corrected Figure 2-19. ■ version 1.1 © October 2008 Altera Corporation and Table 2–6. section. 2–33 Summary of Changes — — Updated document with MAX IIZ information. ...
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... MAX II Device Handbook Chapter 2: MAX II Architecture Document Revision History © October 2008 Altera Corporation ...
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... USERCODE 00 0000 0111 IDCODE 00 0000 0110 (1) HIGHZ 00 0000 1011 © October 2008 Altera Corporation 3. JTAG and In-System Programmability CCINT amount of time has passed. MAX II devices can also CONFIG of the bank where it resides. CCIO Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins ...
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... Table 3–1: (1) HIGHZ, CLAMP, and EXTEST instructions do not disable weak pull-up resistors or bus hold features. (2) These instructions are shown in the 1532 BSDL files, which will be posted on the Altera w Unsupported JTAG instructions should not be issued to the MAX II device as this may put the device into an unknown state, requiring a power cycle to recover device operation ...
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... Using the MAX II device’s JTAG block as a parallel flash loader, with the Quartus II software, to program and verify flash contents provides a fast and cost- effective means of in-circuit programming during test. being used as a parallel flash loader. © October 2008 Altera Corporation Binary IDCODE (32 Bits) (1) Manufacturer ...
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... CCIO CCIO “In-System Programming Clamp” on page 3–6 3–7. Chapter 3: JTAG and In-System Programmability In System Programmability Altera FPGA CONF_DONE nSTATUS nCE DATA0 nCONFIG DCLK to eliminate board conflicts. The in- and © October 2008 Altera Corporation ...
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... JTAG chain. The MAX II 1532 BSDL files will be released on the Altera website when available. Jam Standard Test and Programming Language (STAPL) The Jam STAPL JEDEC standard, JESD71, can be used to program MAX II devices with in-circuit testers, PCs, or embedded processors ...
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... Using Jam STAPL for ISP via an Embedded Processor Real-Time ISP and ISP Clamp for MAX II Devices In System Programmability EPM2210 EPM2210G Unit 3.92 sec 3.40 sec 0.49 sec 0.05 sec 4.41 sec 3.45 sec © October 2008 Altera Corporation ...
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... MAX II devices can be programmed by downloading the information via in-circuit testers, embedded processors, the Altera ByteBlaster™ II, and USB-Blaster cables. BP Microsystems, System General, and other programming hardware manufacturers provide programming support for Altera devices. Check their websites for device support information. Referenced Documents This chapter references the following documents: DC and Switching Characteristics ■ ...
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... June 2004, Corrected Figure 3-1. Added CFM acronym. ■ version 1.1 MAX II Device Handbook Chapter 3: JTAG and In-System Programmability Table 3–1. and Table 3–4. section. Document Revision History Summary of Changes — — — — — — © October 2008 Altera Corporation ...
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... I/O pins do not power the device V internal paths. This is true if the V 1 Altera uses GND as reference for the hot-socketing and I/O buffers circuitry designs. You must connect the GND between boards before connecting the V power supplies to ensure device reliability and compliance to the hot-socketing specifications ...
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... supplies) or power-down event. The hot-socket circuit CCINT CCIO ramps up very slowly during power-up for information pins in any sequence. During CCINT | < 300 A. | < for less below the CCINT CCIO may still be CC © October 2008 Altera Corporation ...
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... This design ensures that the output buffers do not drive when the I/O pad voltage is higher than V CCINT voltage spikes during hot insertion. The V tolerant circuit capacitance. © October 2008 Altera Corporation is within the recommended operating range even though CCINT V CCIO Output Enable ...
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... Larger of VCCIO or VPAD VCCIO well p - substrate Figure 4–3) shows the ESD current discharge path during a Source Gate PMOS N+ Drain P-Substrate Drain Gate N+ NMOS Source GND Ensures 3.3-V Tolerance and Hot-Socket The Larger of Protection VCCIO or VPAD n+ I GND © October 2008 Altera Corporation ...
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... The POR circuit of the MAX II (except MAX IIZ) device continues to monitor the V POR circuit of the MAX IIZ device does not monitor the V device enters into user mode. More details are provided in the following sub-sections. © October 2008 Altera Corporation Figure Source Gate ...
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... Power-On Reset Circuitry and CCINT DC and Switching banks are powered with sufficient is powered more than t after CONFIG banks are powered. CCIO rises back to approximately 1.7 V and V voltage CCINT CCIO voltage sag below 1.4 V CCINT CCINT time has CONFIG © October 2008 Altera Corporation ...
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... I/O tri-states are released. To release clears after tri-states are released, use the DEV_CLRn pin option. To hold the tri-states beyond the power-up configuration time, use the DEV_OE pin option. © October 2008 Altera Corporation MAX II Device Approximate Voltage for SRAM Download Start ...
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... Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices chapter in the MAX II Device Handbook chapter in the MAX II Device and “Power-On sections. Referenced Documents Summary of Changes — Updated document with MAX IIZ information. — — — — — © October 2008 Altera Corporation ...
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... J Notes to Table 5–1: (1) Refer to the Operating Requirements for Altera Devices Data (2) Conditions beyond those listed in Table 5–1 ratings for extended periods of time may have adverse affects on the device. (3) Maximum V for MAX II devices is 4.6 V. For MAX IIG and MAX IIZ devices 2.4 V. ...
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... Commercial range 0 Industrial range –40 Extended range (5) –40 Using MAX II Devices in Multi-Voltage Systems and V are powered. CC INT C CIO © August 2009 Altera Corporation Operating Conditions Maximum Unit 3.60 V 2.625 V 1.89 V 3.60 V 2.625 V 1.89 V 1.575 V 4.0 V ...
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... Hysteresis for Schmitt SCHMITT trigger input ( supply current CCPOWERUP CCINT during power-up (8) R Value of I/O pin pull-up PULLUP resistor during user mode and in-system programming © August 2009 Altera Corporation Typical Maximum — — 100 (Note 1) (Part Conditions Minimum max (2) – ...
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... V, 1 CIO time. CONFIG C CIO Chapter 5: DC and Switching Characteristics Operating Conditions Typical Maximum Unit — 300 µA — — settings (3.3, 2.5, C CIO typical value is S CHM ITT . © August 2009 Altera Corporation ...
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... OH V Low-level output voltage OL Table 5–6. 3.3-V LVCMOS Specifications (Part Symbol Parameter V I/O supply voltage CCIO V High-level input voltage IH V Low-level input voltage IL © August 2009 Altera Corporation MAX II Output Drive 0.0 0.5 2.0 2.5 3.0 3.5 MAX II Output Drive I Characteristics ...
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... Maximum Unit 2.625 V 4.0 V 0.7 V — V — V — V 0.2 V 0.4 V 0.7 V Maximum Unit 1.89 V 2.25 (2) V 0.35 × CIO — V 0.45 V Maximum Unit 1.575 0.3 ( CIO 0.35 × CIO — V 0.25 × CIO maximum of 4.0, as specified © August 2009 Altera Corporation ...
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... High sustaining V < V (minimum current Low overdrive 0 V < V < CIO current High overdrive 0 V < V < CIO current © August 2009 Altera Corporation Minimum Typical — 3.0 3.3 — 0.5 × V — C CIO — –0.5 — 0.9 × V — C CIO — — V ...
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... Evaluating Power in MAX II Devices PowerPlay Power Analysis Timing Model and Specifications MAX II devices timing can be analyzed with the Altera Quartus of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in MAX II devices have predictable internal delays that enable the designer to determine the worst-case timing of any design ...
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... Table 5–13. MAX II Device Timing Model Status Device EPM240 EPM240Z (1) EPM570 EPM570Z (1) © August 2009 Altera Corporation t R4 Logic Element t C4 LUT Delay t t COMB LUT ...
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... MHz 8.0 9.7 9.7 9.7 MHz (4) (4) (4) (4) MHz 100 100 100 100 kHz (5) (5) (5) (5) © August 2009 Altera Corporation ...
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... Minimum clock 166 CLK HL high or low time t Register control — 857 C delay © August 2009 Altera Corporation through Table 5–22 describe the MAX II device internal timing Table 5–15 through Table 5–22 Understanding Timing in MAX II Devices MAX II / MAX IIG –4 Speed –5 Speed – ...
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... Speed Grade Grade Max Min Max Min Max Unit 0 — 0 — — 71 — — 0 — — 71 — — 87 — 90 162 — 174 — 177 279 — 289 — 291 499 — 508 — 512 © August 2009 Altera Corporation Unit ...
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... LVCMOS 3 mA — 207 1.5-V LVCMOS 4 mA — 606 2 mA — 673 3.3-V PCI 20 mA — 71 © August 2009 Altera Corporation (Part MAX II / MAX IIG –4 Speed –5 Speed –6 Speed Grade Grade Grade Min Max Min Max Min — 1,454 — ...
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... Speed –8 Speed Grade Grade Grade Unit — 100 — 100 — ns — 20 — 20 — ns — 20 — 20 — ns — 20 — 20 — ns — 20 — 20 — ns — 100 — 100 — ns — 60 — 60 — ns — 20 — 20 — ns © August 2009 Altera Corporation ...
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... Maximum length of — EPM X busy pulse during an erase t Delay from data — DCO register clock to data register output © August 2009 Altera Corporation MAX II / MAX IIG –4 Speed –5 Speed –6 Speed Grade Grade Grade Max Min Max Min Max Min Max Min Max Min Max — ...
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... Speed –8 Speed Grade Grade Grade Min Max Min Max Min Max 180 — 180 — 180 — — 65 — 65 — 65 250 — 250 — 250 — 250 — 250 — 250 — t DSH © August 2009 Altera Corporation Unit ...
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... Min t — 429 — — 326 — — 330 — LOCA L Note to Table 5–22: (1) The numbers will only be available in a later revision. © August 2009 Altera Corporation ADH 16 Data Bits t t DCLK DSS t DDH t DDS 9 Address Bits t t ACLK AH t ADH ...
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... August 2009 Altera Corporation Unit ...
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... CH high time t Global clock — CL low time t Minimum — CNT global clock period for 16-bit counter © August 2009 Altera Corporation (Part MAX II / MAX IIG –3 Speed –4 Speed –5 Speed Grade Grade Grade Max Min Max Min Max 304.0 — ...
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... MHz © August 2009 Altera Corporation Unit ...
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... Table 5–27. External Timing Input Delay Adders (Part –3 Speed I/O Standard Min 3.3-V LVTTL Without Schmitt — Trigger With Schmitt — Trigger © August 2009 Altera Corporation MAX II / MAX IIG –3 Speed Grade –4 Speed Grade Condition Min Max 10 pF — 7 — ...
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... August 2009 Altera Corporation Unit Unit ...
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... LVCMOS 4 mA — 38,723 2 mA — 41,330 3.3-V PCI 20 mA — 261 © August 2009 Altera Corporation Adders for Fast Slew Rate OD MAX II / MAX IIG –4 Speed –5 Speed –6 Speed Grade Grade Grade Min Max Min Max Min — ...
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... MHz 220 220 220 MHz 188 188 188 MHz 220 220 220 MHz 188 188 188 MHz 200 200 200 MHz 200 200 200 MHz 150 150 150 MHz 304 304 304 MHz © August 2009 Altera Corporation ...
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... JC P TCK clock period for V TCK clock period for V TCK clock period for V t TCK clock high time TCK clock low time JC L © August 2009 Altera Corporation MAX II / MAX IIG –4 Speed –5 Speed Grade Grade Grade 304 304 304 ...
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... This chapter references the following documents: I/O Structure section in the ■ Handbook ■ Hot Socketing and Power-On Reset in MAX II Devices Handbook ■ Operating Requirements for Altera Devices Data Sheet ■ PowerPlay Power Analysis Understanding and Evaluating Power in MAX II Devices ■ Handbook ■ Understanding Timing in MAX II Devices ■ ...
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... August 2005, Updated Figure 5-1. ■ version 1.4 Updated Tables 5-13, 5-16, and 5-26. ■ Removed Note 1 from Table 5-12. ■ © August 2009 Altera Corporation Changes Made Table 5–29, and Table 5–30. 5–2, Table 5–4, Table 5–14, Table 5– ...
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... Table 5-31 is new. ■ June 2004, Updated timing Tables 5-15 through 5-32. ■ version 1.1 MAX II Device Handbook Changes Made parameter in Table 5-4. P ULLUP Chapter 5: DC and Switching Characteristics Document Revision History Summary of Changes — — — © August 2009 Altera Corporation ...
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... The Quartus II software supports the Windows XP/2000/NT, Sun Solaris, Linux Red Hat v8.0, and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink interface. Device Pin-Outs Printed device pin-outs for MAX II devices are available on the Altera website (www.altera.com). Ordering Information Figure 6–1 describes the ordering codes for MAX II devices ...
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... MAX II Device Handbook Chapter 6: Reference and Ordering Information chapter in the MAX II Device Handbook Changes Made 6–1. Referenced Documents Summary of Changes Added information for speed grade –8 — Updated document with MAX IIZ information. — — — © August 2009 Altera Corporation ...