EVAL-AD7376EBZ Analog Devices Inc, EVAL-AD7376EBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD7376EBZ
• Description: Eval Board For AD7376
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7376EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: AD7376
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
DIGITAL INPUTS AND OUTPUTS
POWER SUPPLIES
DYNAMIC CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
TIMING SPECIFICATIONS
Table 3.
Parameter
INTERFACE TIMING CHARACTERISTICS
1
2
3
Typical values represent average readings at 25°C, V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL
measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.
Pb-free parts have a 35 ppm/°C temperature coefficient.
INL and DNL are measured at V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the A terminal. A terminal is open circuit in shutdown mode.
P
Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
Guaranteed by design and not subject to production test.
See Figure 3 for the location of the measured values. All input control voltages are specified with t
Switching characteristics are measured using V
Propagation delay depends on value of V
All dynamic characteristics use V
DISS
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
Power Supply Range
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Rejection Ratio
Bandwidth −3 dB
Total Harmonic Distortion
V
Resistor Noise Voltage
Clock Frequency
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Fall Hold Time
CLK Rise to CS Rise Hold Time
CS Rise to Clock Rise Setup
W
is calculated from (I
Settling Time
6
8
DD
× V
DD
W
) + abs(I
with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. V
DD
6, 9, 10
= 15 V and V
3
SS
DD
× V
, R
1, 2
SS
Pull-Up
). CMOS logic level inputs result in minimum power dissipation.
DD
SS
= 15 V and V
, and C
= −15 V.
Symbol
DD
f
t
t
t
t
t
t
t
t
t
t
CLK
CH
DS
DH
PD
CSS
CSW
RS
CSH0
CSH
CS1
Symbol
V
V
V
V
I
C
V
V
I
I
P
PSRR
BW
THD
t
e
IL
DD
SS
S
= 15 V, and V
N_WB
IH
IL
OH
OL
IL
DD
DD
DISS
, t
L
/V
CL
.
W
SS
SS
= −15 V.
SS
= −15 V.
Conditions
Clock level high or low
R
Rev. C | Page 5 of 20
Pull-Up
Conditions
V
V
R
I
V
Dual-supply range
Single-supply range, V
V
V
V
V
V
R
R
V
V
R
= 2.2 kΩ, C
OL
DD
DD
Pull-Up
IN
IH
IH
IH
IH
IH
AB
AB
A
A
WB
= 1 V rms, V
= 10 V, V
= 1.6 mA, V
= 0 V or 5 V
= 5 V or V
= 5 V or V
= 5 V or V
= 5 V or V
= 5 V or V
= 50 kΩ, code = 0x40
= 100 kΩ, code = 0x40
= 5 V or 15 V
= 5 V or 15 V
= 25 kΩ, f = 1 kHz
= 2.2 kΩ to 5 V
L
B
< 20 pF
= 0 V, ±1 LSB error band
IL
IL
IL
IL
IL
R
LOGIC
= 0 V, V
= 0 V, V
= 0 V, V
= 0 V, V
= 0 V, V
= t
B
= 0 V, f = 1 kHz
F
= 1 ns (10% to 90% of V
= 5 V, V
DD
DD
DD
DD
DD
SS
/V
/V
/V
/V
/V
= 0
SS
SS
SS
SS
SS
DD
= ±15 V
= ±5 V
= ±15 V
= ±5 V
= ±15 V
= 15 V
DD
Min
120
30
20
10
120
150
120
10
120
120
) and timed from a voltage level of 1.6 V.
Min
2.4
4.9
±4.5
4.5
−0.25
Typ
Typ
5
12
±0.1
90
50
0.002
4
2
1
A
= V
Max
4
100
Max
0.8
0.4
±1
±16.5
33
2
25
−0.1
−0.1
31.5
+0.25
DD
and V
AD7376
B
Unit
μA
pF
mW
kHz
kHz
%
nV√Hz
V
V
V
V
V
V
mA
μA
mA
mA
%/%
μs
= 0 V.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns