FM24W256-EGTR Ramtron, FM24W256-EGTR Datasheet - Page 4

• Manufacturer Part Number: FM24W256-EGTR
• Description: EIAJ SOIC8 T&R
• Manufacturer: Ramtron

Stop Condition
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24W256 should
end with a stop condition. If an operation is in
progress when a stop is asserted, the operation will be
aborted. The master must have control of SDA (not a
memory read) in order to assert a stop condition.
Start Condition
A start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All commands should be preceded by a start
condition. An operation in progress can be aborted by
asserting a start condition at any time. Aborting an
operation using the start condition will ready the
FM24W256 for a new operation.
If during operation the power supply drops below the
specified V
start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The acknowledge takes place after the 8
been transferred in any transaction. During this state
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
no-acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the no-acknowledge ceases the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Rev. 1.3
July 2011
SDA
SCL
DD
minimum, the system should issue a
(Master)
Stop
(Master)
Start
th
Figure 3. Data Transfer Protocol
data bit has
(Transmitter)
7
Data bits
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24W256
will continue to place data onto the bus as long as
the receiver sends acknowledges (and clocks). When
a read operation is complete and no more data is
needed, the receiver must not acknowledge the last
byte. If the receiver acknowledges the last byte, this
will cause the FM24W256 to attempt to drive the
bus on the next clock while the master is sending a
new command such as stop.
Slave Address
The first byte that the FM24W256 expects after a
start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the device select address bits, and a bit that specifies
if the transaction is a read or a write.
Bits 7-4 are the device type and should be set to
1010b for the FM24W256. These bits allow other
types of function types to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
address
corresponding value on the external address pins to
select the device. Up to eight FM24W256s can
reside on the same two-wire bus by assigning a
different address to each. Bit 0 is the read/write bit.
R/W=1 indicates a read operation and R/W=0
indicates a write operation.
FM24W256 - 256Kb Wide Voltage I2C F-RAM
6
select
(Transmitter)
Data bit
bits.
0
They
Acknowledge
(Receiver)
must
match
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the