KS8721BL A4 Micrel Inc, KS8721BL A4 Datasheet - Page 9

• Manufacturer Part Number: KS8721BL A4
• Description: 10/100 Base-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-LQFP
• Manufacturer: Micrel Inc

Specifications of KS8721BL A4

• Lead Free Status / Rohs Status: Not Compliant

Strapping Options
Notes:
1. Strap-in is latched during power-up or reset.
2. Ipu = Input w/ internal pull-up.
3. Some devices may drive MII pins that are designated as output (PHY) on power-up, resulting in incorrect strapping values latched at reset. It is rec-
February 2005
KS8721BL/SL
Pin Number
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and float information.
mmended that an external pull-down via 1kΩ resistor be used in these applications to augment the 8721's internal pull-down.
11
21
22
6,5,
9
4,3
25
27
28
29
30
(3)
(3)
(3)
(3)
PHYAD[4:1]/
PCS_LPBK/
ISO/RXER
RMII_BTB
Pin Name
NWAYEN/
RMII/COL
PHYAD0/
DUPLEX/
RXD[0:3]
SPD100/
No FEF/
RXDV
LED2
LED3
INT#
CRS
PD#
(1)
Type
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipu
(2)
Description
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
PU = Enable.
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched
as LED1 the Speed Support in register 4h. (If FXEN is pulled up, the latched value
PHY Address latched at power-up/reset. The default PHY address is 00001.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,
0 means no Far_End _Fault.)
Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU
(default) = Full-duplex. If Duplex is pulled up during reset, this pin is also latched as
the Duplex support in register 4h.
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.
9
M9999-022105
Micrel