KSZ8842-PMQL Micrel Inc, KSZ8842-PMQL Datasheet - Page 44
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KSZ8842-PMQL
Manufacturer Part Number
KSZ8842-PMQL
Description
2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )
Manufacturer
Micrel Inc
Specifications of KSZ8842-PMQL
Controller Type
Ethernet Switch Controller
Interface
PCI
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.5V
Operating Supply Voltage (min)
3.1V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1636 - BOARD EVALUATION KSZ8842-PMQL
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-1513-5
KSZ8842-PMQL
KSZ8842-PMQL
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8842-PMQLI
Manufacturer:
TI
Quantity:
3 100
Micrel, Inc.
MAC DMA Receive Control Register (MDRXC Offset 0x0004)
The MAC DMA receive control register establishes the receive operating modes and commands for the port. This
register should be one of the last CSRs to be written as part of the receive initialization.
The following table shows the register bit fields.
October 2007
31 – 30
29 – 24
23 – 19
8 – 3
Bit
Bit
18
17
16
9
2
1
0
Default
Default
0x00
0x0
0x0
00
0
0
0
0
0
0
0
R/W
R/W
RW
RW
RW
RW
RO
RW
RW
RW
RW
RO
RO
Description
MTFCE MAC Transmit Flow Control Enable
When this bit is set, flow control is enabled. This causes the KSZ8842-
PMQL/PMBL to transmit a PAUSE frame from DMA to switch host MAC when
the Receive Buffer has reached threshold and this bit is enabled. (SGCR3 bit
5 also needs to be enabled).
Note: KSZ8842-PMQL/PMBL is full duplex only for RX/TX buffer.
Reserved
MTEP MAC DMA Transmit Enable Padding
When set, the KSZ8842-PMQL/PMBL automatically adds a padding field to a
packet shorter than 64 bytes.
Note: Setting this bit automatically enables Add CRC feature.
MTAC MAC DMA Transmit Add CRC
When set, the KSZ8842-PMQL/PMBL appends the CRC to the end of the
transmission frame.
MTE MAC DMA TX Enable
When the bit is set, the MDMA TX block is enabled and placed in a running
state. When reset, the transmission process is placed in the stopped state
after completing the transmission of the current frame. The stop transmission
command is effective only when the transmission process is in the running
state.
Description
Reserved
MRBS DMA Receive Burst Size
This field indicates the maximum number of words to be transferred in one
DMA transaction. If reset, the MAC DMA burst size is limited only by the
amount of data stored in the receive buffer before issuing a bus request. The
MRBS can be programmed with the following permissible values: 0,1, 2, 4, 8,
16, or 32.
After reset, the MRBS default is 0, i.e., unlimited.
Reserved
MRUCC MAC Receive UDP Checksum Check
When set, the KSZ8842-PMQL/PMBL will check for correct UDP checksum
for incoming UDP/IP frames at port.
Packets received with incorrect UDP checksum will be discarded.
MRTCG MAC Receive TCP Checksum Check
When set, the KSZ8842-PMQL/PMBL will check for correct TCP checksum for
incoming TCP/IP frames at port.
Packets received with incorrect TCP checksum will be discarded.
MRICG MAC Receive IP Checksum Check
When set, the KSZ8842-PMQL/PMBL will check for correct IP checksum for
incoming IP frames at port.
Packets received with incorrect IP checksum will be discarded.
44
KSZ8842-PMQL/PMBL
M9999-100207-1.5