LMP92001SQE/NOPB National Semiconductor, LMP92001SQE/NOPB Datasheet - Page 25

• Manufacturer Part Number: LMP92001SQE/NOPB
• Description: IC ANALOG MONITOR/CTLR 54LLP
• Manufacturer: National Semiconductor

Specifications of LMP92001SQE/NOPB

• Applications: General Purpose
• Current - Supply: 4mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 54-WFQFN Exposed Pad
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Operating Temperature (max): 125C
• Package Type: LLP EP
• Rad Hardened: No
• Supply Voltage Range: 4.75V To 5.5V
• Operating Temperature Range: -40°C To +125°C
• Digital Ic Case Style: LLP
• No. Of Pins: 54
• Peak Reflow Compatible (260 C): Yes
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMP92001SQE/NOPBTR

16.1.7 Interrupt Subsystem
Device outputs INT1 and INT2 report out of bounds conditions
as determined by the digital window comparator. INT1 and
INT2 are open collector outputs and are active LO. INT1 re-
ports out of bound conditions at ADC channels 1-3, and INT2
16.2 PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM
This subsystem consists of 12 identical DACs whose output
is a function of user programmable registers DACx. This func-
tionality is described in
There are instances where it is necessary to instantaneously
“turn off” the devices downstream of OUTx output, without in-
curring the delay due to the I
transfer. This functionality is described in
Asynchronous Output
Control.
Section 16.2.1 DAC
2
C-compatible data/command
Core.
Section 16.2.3
FIGURE 4. Interrupt System
25
reports out of bound conditions at ADC channels 9-11. Func-
tional diagram of the interrupt system is shown in
Additionally, presence of any out of bound condition is report-
ed in the SGEN register, which can be tested via the I
compatible interface.
16.2.1 DAC Core
The DAC core is based on a Resistive String architecture
which guarantees monotonicity of its transfer function. The
input data is single-registered, meaning that the VOUTx of the
DAC is updated as soon as the data is updated in the DACx
data register at the end of the I
The functional diagram of the DAC Core is shown in
5.
2
C-compatible transaction.
30132735
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Figure
Figure
4.
2
C-