AD9860BST Analog Devices Inc, AD9860BST Datasheet - Page 7

• Manufacturer Part Number: AD9860BST
• Description: IC FRONT-END MIXED-SGNL 128-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9860BST

• Rohs Status: RoHS non-compliant
• Rf Type: LMDS, MMDS
• Features: 10-bit ADCs, 12-bit DACs
• Package / Case: 128-LQFP
• Operating Supply Voltage (max): 3.9V
• Operating Temp Range: -40C to 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

Pin No.
68/70–79 D0A to
80/82–91 D0B to
92
98, 99,
104, 105,
117, 118,
123, 124,
100, 103, AGND
106, 109,
110, 112,
113, 116,
119, 122,
101
102
107
108
111
114
115
120
121
18, 20
23, 32
19, 24,
27, 28, 31
21
22
25
26
29
30
37–48/50 Tx11/Tx13
51
62
*The logic level of the Mode/TxBLANK pin at power up defines the default timing
REV. 0
mode; a logic low configures Normal Operation, logic high configures Alternate
Operation Mode.
Mnemonic
Receive Pins
D9A/D11A
D9B/D11B
RxSYNC
AVDD
REFT_B
REFB_B
VIN+B
VIN–B
VREF
VIN–A
VIN+A
REFB_A
REFT_A
Transmit Pins
AVDD
AGND
REFIO
FSADJ
IOUT–A
IOUT+A
IOUT+B
IOUT–B
to Tx0
TxSYNC
MODE/
TxBLANK* Controls Tx Digital Power Down
Function
10-/12-Bit ADC Output of
Receive Channel A
10-/12-Bit ADC Output of
Receive Channel B
Synchronization Clock for
Channel A and Channel B Rx Paths
Analog Supply Pins
Analog Ground Pins
Top Reference Decoupling for
Channel B ADC
Bottom Reference Decoupling
for Channel B ADC
Receive Channel B Differential (+) Input
Receive Channel B Differential ( ) Input
Internal ADC Voltage Reference
Receive Channel A Differential ( ) Input
Receive Channel A Differential (+) Input
Bottom Reference Decoupling for
Channel A ADC
Top Reference Decoupling for
Channel A ADC
Analog Supply Pins
Analog Ground Pins
Reference Output, 1.2 V Nominal
Full-Scale Current Adjust
Transmit Channel A DAC
Differential ( ) Output
Transmit Channel A DAC
Differential (+) Output
Transmit Channel B DAC
Differential (+) Output
Transmit Channel B DAC
Differential ( ) Output
12-/14-Bit Transmit DAC Data
(Interleaved Data when Required)
Synchronization Input for Transmitter
Configures Default Timing Mode,
PIN FUNCTION DESCRIPTIONS
–7–
Pin No.
10
11, 16
12
13
14
15
17
64
65
1
3, 4, 13
2, 9
5
6
7
8
33, 36, 53, DVDD
59, 61, 66,
93
34, 35, 52, DGND
58, 60, 67,
94
54
55
56
57
63
95
96
97
128
126
125
127
Various Pins
Mnemonic
Clock Pins
DLL_Lock
AGND
NC
AVDD
OSC1
OSC2
CLKSEL
CLKOUT2
CLKOUT1
AUX_ADC_A1 Auxiliary ADC A Input 1
AVDD
AGND
SIGDELT
AUX_DAC_A
AUX_DAC_B
AUX_DAC_C
SCLK
SDO
SDIO
SEN
RESETB
AUX_SPI_do
AUX_SPI_clk
AUX_SPI_csb
AUX_ADC_A2 Auxiliary ADC A Input 2
AUX_ADC_B1
AUX_ADC_B2
AUX_ADC_REF Auxiliary ADC Reference
Auxiliary ADC B Input 1
Auxiliary ADC B Input 2
Function
DLL Lock Indicator Pin
DLL Analog Ground Pins
No Connect
DLL Analog Supply Pin
Single Ended Input Clock
(or Crystal Oscillator Input)
Crystal Oscillator Input
Controls CLKOUT1 Rate
Clock Output Generated from Input
Clock (DLL Multiplier Setting
and CLKOUT2 Divide Factor)
Clock Output Generated from
Input Clock (1 if CLKSEL = 1
or /2 if CLKSEL = 0)
Analog Power Pins
Analog Ground Pins
Digital Output from
Programmable Sigma-Delta
Auxiliary DAC A Output
Auxiliary DAC B Output
Auxiliary DAC C Output
Digital Power Supply Pin
Digital Ground Pin
Serial Bus Clock Input
Serial Bus Data Bit
Serial Bus Data Bit
Serial Bus Enable
Reset (SPI Registers and Logic)
Optional Auxiliary ADC Serial Bus
Data Out Bit
Optional Auxiliary ADC Serial Bus
Data Out Latch Clock
Optional Auxiliary ADC Serial Bus
Chip Select Bit
AD9860/AD9862