AD9861BCP-80 Analog Devices Inc, AD9861BCP-80 Datasheet - Page 43

IC FRONT-END MIXED SGNL 64-LFCSP

AD9861BCP-80

Manufacturer Part Number
AD9861BCP-80
Description
IC FRONT-END MIXED SGNL 64-LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9861BCP-80

Rohs Status
RoHS non-compliant
Rf Type
WLL, WLAN
Features
10-bit ADC(s), 10-bit DAC(s)
Package / Case
64-VFQFN, CSP Exposed Pad

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9861BCP-80
Manufacturer:
ADI
Quantity:
300
Write Operations
The SPI write operation uses the instruction header to config-
ure a 1-byte or 2-byte register write using the 2/n1 byte setting.
The instruction byte followed by the register data is written
serially into the device through the SDIO pin on rising edges of
the interface clock, SCLK. The data can be transferred MSB first
or LSB first depending on the setting of the LSB first register bit.
The write operation is the same regardless of SDIO BiDir
register setting.
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SEN
SEN
SEN
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
t
t
S
S
R/W
A0
INSTRUCTION HEADER (REGISTER N)
INSTRUCTION HEADER (REGISTER N)
t
t
DS
DS
t
t
t
DH
S
DH
A1
R/W
2/1
A2
A5
t
DS
2/1
t
A3
HI
A4
t
t
LO
LO
A4
A5
A3
t
DH
INSTRUCTION HEADER
A5
A2
A4
Figure 78. 1-Byte Serial Register Write in MSB First Mode
Figure 79. 2-Byte Serial Register Write in MSB First Mode
t
Figure 80. 2-Byte Serial Register Write in LSB First Mode
HI
2/1
A1
t
t
CLK
CLK
A3
R/W
t
A0
HI
D0
D7
A2
t
D1
LO
D6
Rev. 0 | Page 43 of 52
REGISTER (N) DATA
A1
REGISTER (N) DATA
t
D2
CLK
D5
A0
D3
D4
D4
D3
D7
Figure 78 to Figure 80 are examples of writing data into the
device. Figure 78 shows a 1-byte write with MSB first; Figure 79
shows a 2-byte write with MSB first; and Figure 80 shows a
2-byte write with LSB first. Note the differences between LSB
and MSB first modes: both the instruction header and data are
reversed, and the second data byte register location is different.
In the default MSB first mode, the second data byte is written to
a decremented register address. In LSB first mode, the second
data byte is written to an incremented register address.
D5
D2
D6
D6
D1
D7
D0 D7
D5
REGISTER DATA
D0
D4
D1
D6
REGISTER (N+1) DATA
REGISTER (N–1) DATA
D3
D2
D5
D3
D4
D2
D4
D3
D1
D5
D2
D6
D0
D1
t
H
D7
D0
t
H
t
DON'T CARE
H
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
03606-0-022
03606-0-023
03606-0-024
AD9861

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