LTC4215CGN#TR Linear Technology, LTC4215CGN#TR Datasheet - Page 11

• Manufacturer Part Number: LTC4215CGN#TR
• Description: IC,Power Control/Management,CMOS,SSOP,16PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4215CGN#TR

• Linear Misc Type: Positive Low Voltage
• Family Name: LTC4215
• Package Type: SSOP N
• Operating Supply Voltage (min): 2.9V
• Operating Supply Voltage (max): 15V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

OPERATION
The LTC4215 is designed to turn a board’s supply voltage
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. During
normal operation, the charge pump and gate driver turn
on an external N-channel MOSFET’s gate to pass power
to the load. The gate driver uses a charge pump that
derives its power from the V
gate driver is an internal 6.5V GATE-to-SOURCE clamp.
During start-up the inrush current is tightly controlled by
using current limit foldback, soft start dI/dt limiting and
output dV/dt limiting.
The current sense (CS) amplifi er monitors the load current
using the difference between the SENSE
and SENSE
rent in the load by pulling back on the GATE-to-SOURCE
voltage in an active control loop when the sense voltage
exceeds the commanded value. The CS amplifi er requires
20μA input bias current from both the SENSE
SENSE
A short circuit on the output to ground results in excessive
power dissipation during active current limiting. To limit
this power, the CS amplifi er regulates the voltage between
the SENSE
If an overcurrent condition persists, the internal circuit
breaker (CB) registers a fault when the sense voltage ex-
ceeds 25mV for more than 20μs in the case of the LTC4215
or 420μs in the case of the LTC4215-2. This indicates to
the logic that it is time to turn off the GATE to prevent
overheating. At this point the start-up TIMER pin voltage
ramps down using the 2μA current source until the volt-
age drops below 0.2V (comparator TM1) which tells the
logic that the pass transistor has cooled and it is safe to
turn it on again if overcurrent auto-retry is enabled. If the
TIMER pin is tied to INTV
to 5 seconds on an internal system timer in the logic.
–
pins.
+
–
and SENSE
pin voltages. The CS amplifi er limits the cur-
–
CC
pins at 75mV.
, the cool-down time defaults
DD
pin. Also included in the
+
(V
DD
for SSOP)
+
and the
The output voltage is monitored using the FB pin and the
Power Good (PG) comparator to determine if the power
is available for the load. The power good condition can be
signaled by the GPIO pin using an open-drain pulldown
transistor. The GPIO pin may also be confi gured to signal
power bad, or as a general purpose input (GP comparator),
or a general purpose open drain output.
The Functional Diagram shows the monitoring blocks of
the LTC4215. The group of comparators on the left side
includes the undervoltage (UV), overvoltage (OV), reset
(RST), enable (EN) and signal on (ON) comparators. These
comparators determine if the external conditions are valid
prior to turning on the GATE. But fi rst the two undervoltage
lockout circuits, UVLO1 and UVLO2, validate the input
supply and the internally generated 3.1V supply, INTV
UVLO2 also generates the power-up initialization to the
logic circuits as INTV
fi xed internal overvoltage comparator, OV2, detects that
V
an overvoltage fault and turns the GATE off.
Included in the LTC4215 is an 8-bit A/D converter. The con-
verter has a 3-input multiplexer to select between the ADIN
pin, the SOURCE pin and the V
An I
also allows the host to poll the device and determine if
faults have occurred. If the ALERT line is confi gured as an
interrupt, the host is enabled to respond to faults in real
time. The typical SDA line is divided into an SDAI (input)
and SDAO (output). This simplifi es applications using an
optoisolator driven directly from the SDAO output. An ap-
plication which uses optoisolation is shown in Figure 14.
The I
and ADR2 pins. These inputs have three states each that
decode into a total of 27 device addresses. ADR1 and
ADR2 are not available in the SSOP package; therefore,
those pins are NC in the address map.
DD
2
is greater than 15.6V, the part immediately generates
2
C interface is provided to read the A/D registers. It
C device address is decoded using the ADR0, ADR1
LTC4215/LTC4215-2
CC
crosses this rising threshold. If the
DD
– SENSE voltage.
11
4215fe
CC
.