WM8805GEDS Wolfson Microelectronics, WM8805GEDS Datasheet
WM8805GEDS
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WM8805GEDS Summary of contents
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... S, left justified, right APPLICATIONS • Surround Sound AV processors and Hi-Fi systems • Music industry applications • DVD-P/DVD-RW • Digital TV http://www.wolfsonmicro.com/enews/ WM8805 Left, Right Justified or DSP 16/20/24 bit word lengths TM and DTS Production Data, September 07, Rev 4.1 Copyright ©2007 Wolfson Microelectronics plc TM . ...
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WM8805 DESCRIPTION .......................................................................................................1 BLOCK DIAGRAM .................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................6 SUPPLY CURRENT ...................................................................................................... 6 ELECTRICAL CHARACTERISTICS ......................................................................6 MASTER CLOCK TIMING......................................................................................7 DIGITAL AUDIO ...
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... Production Data PIN CONFIGURATION ( Top View ) ORDERING INFORMATION TEMPERATURE DEVICE RANGE WM8805GEDS -25 to +85 WM8805GEDS/R -25 to +85 Note: Reel quantity = 2,000 w PACKAGE SENSITIVITY LEVEL 28-lead SSOP o C (Pb-free) 28-lead SSOP o C (Pb-free, tape and reel) MOISTURE PEAK SOLDERING TEMPERATURE o 260 C MSL1 o 260 C MSL1 PD Rev 4 ...
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WM8805 PIN DESCRIPTION PIN NAME 1 DVDD 2 RX1 3 RX0 4 SCLK 5 GPO0 / SWIFMODE 6 GPO1 7 SDIN / HWMODE 8 SDOUT / GPO7 9 CSB / GPO2 10 RESETB 11 PVDD 12 PGND 13 CLKOUT 14 ...
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Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
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WM8805 RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range Ground PLL supply range Ground Note: 1. PLL and digital supplies must always be within 0.3V of each other. 2. PLL and digital grounds must always be within 0.3V of each other. ...
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Production Data MASTER CLOCK TIMING MCLK Figure 1 Master Clock Timing Requirements Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T PARAMETER System Clock Timing Information – Slave Mode MCLK System clock cycle time ...
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WM8805 DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK LRCLK DIN DOUT Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T PARAMETER SYMBOL Audio Data Input ...
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Production Data CONTROL INTERFACE – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T PARAMETER Program Register Input Information SCLK rising edge ...
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WM8805 CONTROL INTERFACE – 2-WIRE MODE t STHO SDIN SCLK t SCY Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T PARAMETER Program Register ...
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Production Data DEVICE DESCRIPTION INTRODUCTION FEATURES • • • • • • • • • • The WM8805 is an IEC-60958 compatible S/PDIF transceiver with support for up to eight received S/PDIF data streams and one transmitted S/PDIF data stream. ...
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WM8805 Frame 0 preamble Figure 6 S/PDIF Format POWER UP CONFIGURATION The operating mode of the WM8805 is dependent upon the state of SDIN, SCLK, SDOUT, CSB and GPO0 when the device is powered hardware reset occurs. ...
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Production Data When the device powers up, all power up configuration pins are configured as inputs for a minimum of 9.4us and a maximum of 25.6us following the release of the external reset. The times are based on 27MHz and ...
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WM8805 CONTROL INTERFACE OPERATION Control of the WM8805 is implemented in either hardware control mode or software control mode. The method of control is determined by sampling the state of the SDIN/HWMODE pin at power hardware ...
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Production Data 3-WIRE SERIAL CONTROL MODE REGISTER READ-BACK Not all registers can be read. Only the device ID (registers R0, R1 and R2) and the status registers can be read. These status registers are labelled as “read only” in the ...
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WM8805 Figure 10 3-Wire Control Interface Read-Back Method 2 2-WIRE SERIAL CONTROL WITH READ-BACK MODE The WM8805 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus and each device has a unique ...
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Production Data Figure 12 2-Wire Serial Control Interface Multi-Write The WM8805 has two possible device addresses, which can be selected using the CSB pin during hardware reset. Table 11 2-Wire Interface Address Selection 2-WIRE SERIAL CONTROL MODE -REGISTER READ-BACK The ...
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WM8805 SOFTWARE REGISTER RESET Writing to register 0000000 will reset the WM8805. This will reset all register bits to their default values. Note that the WM8805 is powered down by default so writing to this register will power down the ...
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Production Data DIGITAL ROUTING CONTROL See page 20 for a full description of the signal routing options available in the WM8805. In Software control mode the values set in registers TXSRC and RXINSEL determine the S/PDIF Rx data source and ...
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WM8805 DIGITAL ROUTING CONTROL Figure 15 Digital Routing Paths within the WM8805 Digital signal routing within the WM8805 is controlled by two registers, RXINSEL and TXSRC. RXINSEL selects the S/PDIF input which is passed through the clock and data recovery ...
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Production Data MASTER CLOCK AND PHASE LOCKED LOOP SOFTWARE MODE INTERNAL CLOCKING The WM8805 is equipped with a comprehensive clocking scheme that provides maximum flexibility and function and many configurable routing possibilities for the user in software mode. An overview ...
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WM8805 The oscillator uses a Pierce type oscillator drive circuit. This circuit requires an external crystal and appropriate external loading capacitors. The oscillator circuit contains a bias generator within the WM8805 and hence an external bias resistor is not required. ...
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Production Data REGISTER ADDRESS R3 PLL1 03h R4 PLL2 04h R5 PLL3 05h R6 PLL4 06h Table 21 User Mode PLL_K and PLL_N Multiplier Control PLL CONFIGURATION The PLL performs a configurable frequency multiplication of the input clock signal (f ...
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WM8805 REGISTER ADDRESS R6 PLL4 06h R7 PLL5 07h Table 22 Pre and Post PLL Clock Divider Control PLL CONFIGURATION EXAMPLE Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and the required MCLK frequency ...
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Production Data OSC PRE SCALE CLK (MHz) (MHz) (MHz 98.304 98.304 98.304 98.304 98.304 90.3168 90.3168 ...
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WM8805 REGISTER ADDRESS R28 AIFRX 1Ch Table 25 Audio Interface Mode Select When MCLK is configured as an output, the MCLK source and rate can be selected using the control bits shown in Table 26. The MCLK rate select can ...
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Production Data REGISTER ADDRESS R7 PLL5 07h R8 PLL6 08h Table 29 Clock Output (CLKOUT) Control S/PDIF TRANSMITTER When the S/PDIF transmitter is enabled and configured (using TXSRC) to use the S/PDIF received data, the S/PDIF transmitter is clocked from ...
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WM8805 The specified f reception of specific S/PDIF sample rates are as follows: • • The FREQMODE[1:0] bits are automatically controlled by the S/PDIF receiver when the receiver is enabled and do not need to be configured in any particular ...
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Production Data TO CONFIGURE THE SYSTEM WHEN CLOCKING MODE (SAMPLE RATE) CHANGES TO OR FROM MODE 1 (176.4/192KHZ): Any sample rate change between clocking modes (for example, from 44.1kHz (mode 3) to 192kHz (mode 1)) will be flagged to the ...
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WM8805 HARDWARE MODE INTERNAL CLOCKING In hardware mode, the user has no access to the internal clocking control registers and hence a default configuration is loaded at reset to provide maximum functionality. An overview of the hardware mode clocking scheme ...
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Production Data S/PDIF TRANSMITTER The S/PDIF transmitter generates the S/PDIF frames, and outputs on the TX0 pin. The audio data for the frame can be taken from one of two sources, selectable using the TXSRC register. The transmitter can be ...
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WM8805 PARITY BIT This bit maintains even parity for data as a means of basic error detection generated by the transmitter. REGISTER BIT ADDRESS R18 0 CON/PRO SPDTX1 12h 1 2 5:3 DEEMPH[2:0] 7:6 CHSTMODE Table 34 S/PDIF ...
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Production Data REGISTER BIT ADDRESS R20 3:0 SPDTX3 14h 5:4 CHNUM1[1:0] 7:6 CHNUM2[1:0] Table 36 S/PDIF Transmitter Channel Bit Control Register 3 REGISTER BIT ADDRESS R21 3:0 SPDTX4 15h 5:4 CLKACU[1:0] Table 37 S/PDIF Transmitter Channel Status Bit Control Register ...
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WM8805 REGISTER BIT ADDRESS R22 0 SPDTX5 16h 3:1 7:4 ORGSAMP Table 38 S/PDIF Transmitter Channel Status Bit Control Register 5 S/PDIF RECEIVER INPUT SELECTION The S/PDIF receiver has dedicated inputs. These inputs can be configured as ...
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Production Data REGISTER BIT ADDRESS R29 5 SPDRX1 1Ch 6 7 R30 1 PWRDN 1Eh R8 2:0 PLL6 08h R9 7:0 SPDMODE 09h Table 39 S/PDIF Receiver Input Selection Registers AUDIO DATA HANDLING The S/PDIF receiver recovers the data and ...
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WM8805 CHANNEL STATUS DATA The channel status bits are recovered from the incoming data stream and are used to control various functions of the device. The S/PDIFRx interface always receives 24 bits of data in bits ...
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Production Data REGISTER BIT ADDRESS R13 0 RXCHAN1 0Dh (read-only 5:4 7:6 CHSTMODE Table 40 S/PDIF Receiver Channel Status Register 1 REGISTER BIT ADDRESS R14 7:0 CATCODE RXCHAN2 0Eh (read-only) Table 41 S/PDIF Receiver Channel Status Register ...
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WM8805 REGISTER BIT ADDRESS R16 3:0 RXCHAN4 10h 5:4 CLKACU[1:0] (read-only) Table 43 S/PDIF Receiver Channel Status Register 4 REGISTER BIT ADDRESS R17 0 RXCHAN5 11h (read-only) 3:1 RXWL[2:0] 7:4 ORGSAMP Table 44 S/PDIF Receiver Channel Status Register 5 Note ...
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Production Data S/PDIF RECEIVER STATUS FLAGS There are several S/PDIF receiver status flags which are recorded by the WM8805. The flags are described in Table 45. These flags are available via GPIO pins or status registers. FLAG UNLOCK Unlock Flag ...
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WM8805 NON_AUDIO Non-Audio Flag Logical OR of PCM_N and AUDIO_N CSUD Channel Status Update Indicates that channel status registers have updated and may be read back over the serial interface. DEEMPH De-emphasis Flag 0 = Recovered data has no pre-emphasis ...
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Production Data INTERRUPT GENERATION The INT_N flag indicates that a change of status has occurred on one or more of the UNLOCK, INVALID, TRANS_ERR, CSUD, NON_AUDIO, CPY_N, REC_FREQ or DEEMPH status flags. To identify which flag caused the interrupt, the ...
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WM8805 Where the INT_N has been asserted by an update signal (UPD_NON_AUDIO, UPD_CPY_N, UPD_REC_FREQ, UPD_UNLOCK or UPD_DEEMPH) the S/PDIF Status Register (SPDSTAT) can be interrogated to establish the updated value of the flag. REGISTER BIT ADDRESS R12 0 SPDSTAT 0Ch ...
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Production Data ERROR HANDLING IN SOFTWARE MODE When the TRANS_ERR flag is asserted, it indicates that the recovered Rx S/PDIF sub-frame is corrupted. This corruption can due to a BI-Phase error, a parity error or a pre-amble error. When the ...
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WM8805 NON-AUDIO DETECTION The SPDIF payload can contain PCM data for audio or non-audio applications. In the case where the payload contains the 96 bit synchronization code defined in IEC61937 then this indicates that the payload contains data which is ...
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Production Data DIGITAL AUDIO INTERFACE Audio data is transferred to and from the WM8805 via the digital audio interface. Data from the digital audio interface transmitter may be passed to the S/PDIF transmitter or data from the S/PDIF receiver may ...
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WM8805 AUDIO DATA FORMATS Five interface formats are supported: • Left Justified Mode • Right Justified Mode 2 • Mode • DSP Mode A • DSP Mode B The MSB is sent first in all formats. Word lengths ...
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Production Data RIGHT JUSTIFIED MODE In Right Justified Mode, the LSB of DIN is sampled by the WM8805 on the rising edge of BCLK preceding an LRCLK transition. The LSB of the output data (DOUT) changes on the falling edge ...
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WM8805 DSP MODE A In DSP Mode A, the MSB of the left channel data is sampled by the WM8805 on the second rising edge of BCLK following an LRCLK rising edge. The right channel data follows the left channel ...
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Production Data ‘WITH FLAGS’ MODE The following diagrams illustrate the position of the status flags within the audio sample for each audio data format when ‘With Flags’ mode is enabled. With flags mode is only available on pin DOUT. The ...
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WM8805 Figure 26 DSP Mode A ‘With Flags’ Figure 27 DSP Mode B ‘With Flags’ w Production Data PD Rev 4.1 September 07 50 ...
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Production Data AUDIO INTERFACE CONTROL The register bits controlling the audio interface are summarised below. Note that dynamically changing the audio data format may cause erroneous operation, and hence is not recommended. REGISTER BIT ADDRESS R29 SPDIFRX1 1Dh R27 1:0 ...
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WM8805 Note 6: MAXWL and RXWL[2:0] bits in recovered channel status data are used to truncate digital audio interface transmitted data. The truncation replaces the lower data bits with 0. Refer to received channel status bit description. w Production Data ...
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Production Data REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8805 can be configured using the Control Interface. Any unused bits which are not ...
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WM8805 REGISTER BIT ADDRESS R00 RST/DEVID1 7:0 00h R01 DEVID2 01h 7:0 (read only) R02 3:0 DEVREV 02h R3 7:0 PLL1 03h R4 7:0 PLL2 04h R5 5:0 PLL3 05h R6 3:0 PLL4 06h w LABEL DEFAULT RESET - DEVID2 ...
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Production Data REGISTER BIT ADDRESS R7 1:0 PLL5 07h 5:4 w LABEL DEFAULT MODE[1: FRACEN 1 3 MCLKDIV 0 CLKOUTDIV[1:0] 01 WM8805 DESCRIPTION PLL Post-scale Divider Select Selects the PLL output divider value in conjunction with MCLKDIV and ...
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WM8805 REGISTER BIT ADDRESS R8 2:0 PLL6 08h R9 7:0 SPDMODE 09h R10 7:0 INTMASK 0Ah w LABEL DEFAULT RXINSEL[2:0] 000 3 CLKOUTSRC 1 4 CLKOUTDIS 1 5 FILLMODE 0 6 ALWAYSVALID 0 7 MCLKSRC 0 SPDIFINMODE 11111111 MASK[7:0] 00000000 ...
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Production Data REGISTER BIT ADDRESS R11 INTSTAT 0Bh (read-only) R12 SPDSTAT 0Ch (read-only) w LABEL DEFAULT 0 - UPD_UNLOCK 1 - INT_INVALID 2 - INT_CSUD 3 - INT_TRANS_ERR 4 - UPD_NON_AUDIO 5 - UPD_CPY_N 6 - UPD_DEEMPH 7 - UPD_REC_FREQ ...
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WM8805 REGISTER BIT ADDRESS R13 RXCHAN1 0Dh (read-only) 5:4 7:6 R14 7:0 RXCHAN2 0Eh (read-only) R15 3:0 RXCHAN3 0Fh (read-only) 5:4 7:6 R16 3:0 RXCHAN4 w LABEL DEFAULT 5:4 REC_FREQ -- [1:0] 6 UNLOCK - 0 CON/PRO 0 1 AUDIO_N ...
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Production Data REGISTER BIT ADDRESS 10h 5:4 (read-only) R17 RXCHAN5 11h (read-only) 3:1 7:4 R18 SPDTX1 12h 5:3 7:6 R19 7:0 SPDTX2 13h R20 3:0 SPDTX3 14h 5:4 w LABEL DEFAULT CLKACU[1: MAXWL 1 RXWL[2:0] 000 ORGSAMP 0000 ...
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WM8805 REGISTER BIT ADDRESS 7:6 R21 3:0 SPDTX4 15h 5:4 R22 SPDTX5 16h 3:1 7:4 R23 3:0 GPO01 7:4 17h R24 3:0 GPO23 7:4 18h R25 3:0 GPO45 7:4 19h R26 3:0 w LABEL DEFAULT CHNUM2[1:0] 00 FREQ[3:0] 0001 CLKACU[1:0] ...
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Production Data REGISTER BIT ADDRESS GPO67 7:4 1Ah R27 1:0 AIFTX 1Bh 3:2 R28 1:0 AIFRX 1Ch 3:2 w LABEL DEFAULT GPO7[3:0] 0100 AIFTX_FMT[1:0] 10 AIFTX_WL[1: AIFTX_BCP 0 5 AIFTX_LRP 0 AIFRX_FMT[1:0] 10 AIFRX_WL[1: AIFRX_BCP 0 ...
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WM8805 REGISTER BIT ADDRESS R29 2:0 SPDRX1 1Dh R30 PWRDN 1Eh w LABEL DEFAULT READMUX 000 [2:0] 3 CONT 0 4 WITHFLAG 0 5 SPDGPO 0 6 WL_MASK 0 7 SPD_192K_EN 1 0 PLLPD 1 1 SPDIFRXPD 1 2 SPDIFTXPD ...
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Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 28 Recommended External Components for Hardware Control Mode Figure 29 Recommended External Components for Software Control Mode w WM8805 PD Rev 4.1 September 07 63 ...
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WM8805 PACKAGE DIMENSIONS DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm Dimensions Symbols (mm) MIN NOM A ----- A 0. 1.65 1. 0.22 c 0.09 D 9.90 10.20 ...
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... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...