WM8805GEDS Wolfson Microelectronics, WM8805GEDS Datasheet - Page 51

• Manufacturer Part Number: WM8805GEDS
• Description: Audio Transmitters, Receivers, Transceivers 8:1 Digi. Interface Transcvr with PLL
• Manufacturer: Wolfson Microelectronics

Specifications of WM8805GEDS

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Production Data
Note 2: In 24 bit I
Table 56 Audio Interface Control
Note 1: S/PDIF data frames contain a maximum of 24-bits of audio data
Note 3: 24 bit Right Justified ‘With Flags’ Mode is not supported.
Note 4: Must be set to the same value as AIFTX_BCP.
Note 5: Must be set to the same value as AIFTX_LRP.
REGISTER
ADDRESS
SPDIFRX1
AIFRX
AIFTX
R29
1Dh
R27
R28
1Ch
1Bh
AUDIO INTERFACE CONTROL
The register bits controlling the audio interface are summarised below. Note that dynamically
changing the audio data format may cause erroneous operation, and hence is not recommended.
cycles). If exactly 32 BCLK cycles occur in one LRCLK (16 high, 16 low) the chip will auto
detect and operate in 16 bit data word length mode.
for a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles (48 BCLK
1:0
3:2
4
5
BIT
1:0
3:2
4
4
5
2
S mode, any data width of 24 bits or less is supported provided that LRCLK is high
AIFTX_FMT[1:0]
AIFRX_FMT[1:0]
AIFRX_WL[1:0]
AIFTX_WL[1:0]
AIFRX_BCP
AIFTX_BCP
AIFRX_LRP
WITHFLAG
AIFTX_LRP
LABEL
DEFAULT
10
01
10
01
0
0
0
0
0
‘With Flags’ Mode Select
0: ‘With Flags’ Mode disabled (see Note 3)
1: ‘With Flags’ Mode enabled
Audio Data Format Select
11: DSP mode
10: I
01: Left justified mode
00: Right justified mode
Audio Data Word Length
11: 24 bits (see notes 1/2/3/6)
10: 24 bits (see notes 1/2/3/6)
01: 20 bits
00: 16 bits
BCLK invert (for master and slave modes)
0 = BCLK not inverted
1 = BCLK inverted
Right, left and I
DSP mode select
1 = invert LRCLK polarity / DSP Mode B
0 = normal LRCLK polarity / DSP Mode A
Audio Data Format Select
11: DSP mode
10: I
01: Left justified mode
00: Right justified mode
Audio Data Word Length
11: 24 bits (see note 1/2/3/6)
10: 24 bits
01: 20 bits
00: 16 bits
BCLK Invert (for master and slave modes)
0 = BCLK not inverted
1 = BCLK inverted
See Note 4
Right, left and I
DSP mode select
1 = invert LRCLK polarity / DSP Mode B
0 = normal LRCLK polarity / DSP Mode A
See Note 5
2
2
S mode
S mode
2
2
DESCRIPTION
S modes – LRCLK polarity and
S modes – LRCLK polarity and
PD Rev 4.1 September 07
WM8805
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