CS493263-CLZ Cirrus Logic Inc, CS493263-CLZ Datasheet - Page 4

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CS493263-CLZ

Manufacturer Part Number
CS493263-CLZ
Description
Audio DSPs IC Multi-Standard Audio Decoder
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS493263-CLZ

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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LIST OF TABLES
4
Figure 18. Motorola
Figure 19. SPI Write Flow Diagram ...................................................................................... 37
Figure 20. SPI Read Flow Diagram ...................................................................................... 37
Figure 21. SPI Timing ........................................................................................................... 39
Figure 22. I2C® Write Flow Diagram .................................................................................... 40
Figure 23. I2C® Read Flow Diagram ................................................................................... 41
Figure 24. I2C® Timing ........................................................................................................ 42
Figure 24. Intel Mode, One-Byte Write Flow Diagram .......................................................... 46
Figure 25. Intel Mode, One-Byte Read Flow Diagram .......................................................... 47
Figure 26. Motorola Mode, One-Byte Write Flow Diagram ................................................... 48
Figure 27. Motorola Mode, One-Byte Read Flow Diagram .................................................. 48
Figure 28. Typical Parallel Host Mode Control Write Sequence Flow Diagram ................... 49
Figure 29. Typical Parallel Host Mode Control Read Sequence Flow Diagram ................... 50
Figure 30. External Memory Interface .................................................................................. 53
Figure 31. External Memory Read (16-bit address) ............................................................. 53
Figure 32. External Memory Write (16-bit address) .............................................................. 53
Figure 33. Typical Serial Boot and Download Procedure ..................................................... 55
Figure 34. Typical Parallel Boot and Download Procedure .................................................. 56
Figure 35. Autoboot Timing Diagram .................................................................................... 58
Figure 36. Autoboot Sequence ............................................................................................. 59
Figure 37. Autoboot INTREQ Behavior ................................................................................ 60
Figure 38. Fast Autoboot Sequence Using GFABT Codes .................................................. 62
Figure 39. Performing a Reset ............................................................................................. 64
Figure 40. Non-Paged Memory ............................................................................................ 65
Figure 41. Example Contents of a Paged 32 Kilobytes External Memory ............................ 66
Figure 42. CDB49300-MEMA.0 Daughter Card for the CDB4923/30-REV-A.0 ................... 67
Figure 43. I
Figure 44. Left Justified Format (Rising Edge Valid SCLK) .................................................. 69
Figure 45. Multichannel Format ............................................................................................ 70
Table 1. PLL Filter Component Values................................................................................. 28
Table 2. Host Modes ............................................................................................................ 36
Table 3. SPI Communication Signals ................................................................................... 36
Table 4. I
Table 5. Parallel Input/Output Registers............................................................................... 45
Table 6. Intel Mode Communication Signals ........................................................................ 46
Table 7. Motorola Mode Communication Signals................................................................. 47
Table 8. Memory Interface Pins............................................................................................ 51
Table 9. Boot Write Messages ............................................................................................. 54
Table 10. Boot Read Messages ........................................................................................... 54
Table 11. Reduced Autoboot Times using GFABT8.LD, GFABT6.LD, and GFABT4.LD on a
Table 12. Memory Requirements for Example 5.1, 6.1 and 7.1 Channel Systems.............. 65
Table 13. Digital Audio Input Port......................................................................................... 70
Table 14. Compressed Data Input Port ................................................................................ 70
Table 15. Digital Audio Output Port ...................................................................................... 72
Table 16. MCLK/SCLK Master Mode Ratios ........................................................................ 72
Table 17. Output Channel Mapping...................................................................................... 72
Table 18. Input Data Type Configuration
Table 19. Input Data Format Configuration
2
CS493264-CL Rev. G DSP................................................................................... 61
(Input Parameter A) .............................................................................................. 75
(Input Parameter B) .............................................................................................. 75
C® Communication Signals ................................................................................. 38
2
S Format ........................................................................................................... 69
®
Parallel Control Mode ......................................................................... 34
CS49300 Family DSP
DS339F7

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