CS493263-CLZ Cirrus Logic Inc, CS493263-CLZ Datasheet - Page 49

• Manufacturer Part Number: CS493263-CLZ
• Description: Audio DSPs IC Multi-Standard Audio Decoder
• Manufacturer: Cirrus Logic Inc

Specifications of CS493263-CLZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

either Read_Byte_MOT() or Read_Byte_INT(),
and ‘Write_Byte_*()’ is a generic reference to
Write_Byte_MOT() or Write_Byte_INT().
shows a typical write sequence. The protocol
presented in
detail.
1) When the host is communicating with the
2) In order to determine whether the CS493XX is
DS339F7
Figure 28. Typical Parallel Host Mode Control
CS493XX, the host must verify that the DSP is
ready to accept a new control byte. If the DSP
is in the midst of an interrupt service routine, it
will be unable to retrieve control data from the
Host Message Register. Please note that
‘Read_Byte_*()’
generic references to either the Intel or
Motorola communication protocol.
If the most recent control byte has not yet
been read by the DSP, the host must not
write a new byte.
ready to accept a new control byte the host
must check the HINBSY bit of the Host Control
Register (bit 2). If HINBSY is high, then the
DSP is not prepared to accept a new control
WRITE_BYTE_*(HOST MESSAGE REGISTER)
READ_BYTE_*(HOST CONTROL REGISTER)
YES
Write Sequence Flow Diagram
Figure 28
MORE BYTES
TO WRITE?
HINSBY==1
FINISHED
and
will now be described in
NO
NO
‘Write_Byte_*()’
Figure 28
YES
are
3) The host knows that the DSP is ready for a new
4) If the host would like to write any more control
6.2.3.2. Control Read in a Parallel Host
Mode
When reading control data from the CS493XX, the
same protocol is used whether the host is reading
a single byte or a 6 byte message.
During the boot procedure, a handshaking protocol
is used by the CS493XX. This handshake consists
of a 3 byte write to the CS493XX followed by a 1
byte response from the DSP. The host must read
the response byte and act accordingly. The boot
procedure is discussed in
on page
During regular operation (at run-time), the
responses from the CS493XX will always be 6
bytes in length.
The example shown in this section can be used for
any control read situation. The generic function
‘Read_Byte_*()’ is used in the following example
as
Read_Byte_MOT()
Figure 29
protocol presented in
described in detail.
1) Optionally, INTREQ going low may be used as
2) The host reads the Host Control Register
byte, and the host should poll the Host Control
Register again. If HINBSY is low, then the host
may write a control byte into the Host Message
Register.
control byte at this point and should write the
control byte to the Host Message Register
(A[1:0] = 00b).
bytes to the CS493XX, the host should once
again poll the Host Control Register (return to
step 1).
an interrupt to the host to indicate that the
CS493XX has an outgoing message. Even
with the use of INTREQ, HOUTRDY must be
checked to insure that bytes are ready for the
host during the read process. Please note that
INTREQ does not go low to indicate an
outgoing message during boot.
(A[1:0] = 01b) in order to determine the state of
a
54.
generalized
shows a typical read sequence. The
CS49300 Family DSP
or
Figure 29
reference
Section 8.1, “Host Boot”
Read_Byte_INT().
will now be
to
either
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