SAA7709H/N103/S420 NXP Semiconductors, SAA7709H/N103/S420 Datasheet - Page 12

• Manufacturer Part Number: SAA7709H/N103/S420
• Description: Audio DSPs Car radio Digital Signal Processor
• Manufacturer: NXP Semiconductors

Specifications of SAA7709H/N103/S420

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935269693557

NXP Semiconductors
11. Dynamic characteristics
Table 13.
V
T
V
ADC0808S125_ADC0808S250_3
Product data sheet
Symbol
Clock timing input: pins CLK+ and CLK
f
f
t
Timing output: pins D0 to D7 and IR
t
t
t
Timing complete conversion signal: pin CCS; see
f
t
3-state output delay time: pins CCS, IR and D7 to D0
t
t
t
t
Analog signal processing (50 % clock duty factor); see
INL
DNL
E
E
B
THD
N
S/N
clk(min)
clk(max)
w(clk)
d(s)
h(o)
d(o)
CCS(max)
d(CCS)
dZH
dZL
dHZ
dLZ
amb
CCA
CCA
O
G
th(RMS)
= 40 C to +85 C; V
= 3.0 V to 3.6 V; V
= 3.3 V, V
Dynamic characteristics
Parameter
minimum clock frequency
maximum clock frequency
clock pulse width
sampling delay time
output hold time
output delay time
maximum CCS frequency
CCS delay time
float to active HIGH delay time
float to active LOW delay time
active HIGH to float delay time
active LOW to float delay time
integral non-linearity
differential non-linearity
offset error
gain error
bandwidth
total harmonic distortion
RMS thermal noise
signal-to-noise ratio
CCD
= V
CCO
CCD
i(IN)
= 1.8 V, T
= 1.65 V to 1.95 V; V
V
i(INN)
amb
[1]
= 2.0 V
; see
= 25 C and C
Conditions
f
1.8 V CMOS clock
LVDS clock
1.8 V CMOS clock
LVDS clock
1.8 V CMOS clock
LVDS clock
DEL0 = HIGH; DEL1 = LOW
DEL0 = LOW; DEL1 = HIGH
DEL0 = HIGH; DEL1 = HIGH
f
f
missing code guaranteed
V
T
spread from device to device;
V
T
f
input
f
f
shorted input; f
f
f
clk
clk
clk
clk
clk
clk
clk
clk
Figure 5
amb
amb
CCA
CCA
CCO
Rev. 03 — 24 February 2009
0.5 dB; V
= 125 MHz
= 20 MHz; f
= 20 MHz; f
= 125 MHz; 3 dB; full-scale
= 125 MHz; f
= 250 MHz; f
= 125 MHz; f
= 250 MHz; f
= 25 C; output code = 127
= 25 C
= 3.3 V; V
= 3.3 V; V
= 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together;
Figure 6
L
= 10 pF; unless otherwise specified.
I(cm)
Section 12
i
i
clk
CCD
CCD
= 21.4 MHz
= 21.4 MHz; no
i
i
i
i
= 0.95 V; V
= 78 MHz
= 125 MHz
= 78 MHz
= 125 MHz
= 125 MHz
= 1.8 V;
= 1.8 V;
Single 8-bit ADC, up to 125 MHz or 250 MHz
FSIN
= 0 V; typical values are measured at
ADC0808S125/250
[2]
[3]
[4]
Min
-
250
1.8
-
-
3.3
4.2
-
-
125
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
-
-
-
1.3
1.65
4.4
4.8
5.4
5.8
-
0.3
0.8
1.9
2.1
2.2
3.3
2.9
2.5
1.85
560
0.5
48
47
0.82
0.4
53
53
Max
1
-
-
-
-
-
-
6.9
7.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2009. All rights reserved.
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
LSB
LSB
mV
%
MHz
dB
dB
LSB
dBc
dBc
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