Si5338K-A-GM Silicon Laboratories Inc, Si5338K-A-GM Datasheet - Page 33

• Manufacturer Part Number: Si5338K-A-GM
• Description: Clock Generators & Support Products I2C-PRGRMBL clock generatr 0.16-700MHz
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5338K-A-GM

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin #
5,6
10
12
13
14
11
7
8
9
Pin Name
IN5/IN6
VDDO3
CLK3B
CLK3A
CLK2B
CLK2A
INTR
VDD
SCL
VDD
VDD
I/O
O
O
O
O
O
I
I
Table 15. Si5338 Pin Descriptions (Continued)
Signal Type
Open Drain
LVCMOS
Supply
Supply
Multi
Multi
Multi
Multi
Multi
FDBK/FDBKB.
These pins can be used as a differential feedback input in zero
delay mode or as a secondary clock input. See section 3.2,
Figure 3, for termination details. See "3.10.6. Zero-Delay Mode" on
page 26 for zero delay mode set-up. Inputs to these pins must be
ac-coupled.
When not in use, leave IN5 unconnected and IN6 connected to
GND.
Core Supply Voltage.
This is the core supply voltage, which can operate from a 1.8, 2.5,
or 3.3 V supply. A 0.1 µF bypass capacitor should be located very
close to this pin.
Interrupt.
A typical pullup resistor of 1–4 k is used on this pin. This pin can
be pulled up to a supply voltage as high as 3.6 V regardless of the
other supply voltages on pins 7, 11, 15, 16, 20, and 24. The inter-
rupt condition allows the pull up resistor to pull the output up to the
supply voltage.
Output Clock B for Channel 3.
May be a single-ended output or half of a differential output with
CLK3A being the other differential half. If unused, leave this pin
floating.
Output Clock A for Channel 3.
May be a single-ended output or half of a differential output with
CLK3B being the other differential half. If unused, leave this pin
floating.
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK3A,B. A 0.1 µF
capacitor must be located very close to this pin. If CLK3 is not
used, this pin must be tied to VDD (pin 7, 24).
I
This is the serial clock input for the I
pin is required. Typical values would be 1–4 k. See the I
spec for more information. This pin is 3.3 V tolerant regardless of
the other supply voltages on pins 7, 11, 15, 16, 20, 24. See Regis-
ter 27.
Output Clock B for Channel 2.
May be a single-ended output or half of a differential output with
CLK2A being the other differential half. If unused, leave this pin
floating.
Output Clock A for Channel 2.
May be a single-ended output or half of a differential output with
CLK2B being the other differential half. If unused, leave this pin
floating.
2
C Serial Clock Input.
Rev. 1.0
Description
2
C bus. A pullup resistor at this
Si5338
2
C bus
33