MAX3872EGJ Maxim Integrated Products, MAX3872EGJ Datasheet - Page 12

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MAX3872EGJ

Manufacturer Part Number
MAX3872EGJ
Description
Timers & Support Products Multirate Clock and Data Recovery with L
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX3872EGJ

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The MAX3872 has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
maintaining a BER better than 10
is tested using a 2
and zeros inserted in the pattern. A CID tolerance of
2000 bits is typical.
The EP 32-pin QFN incorporates features that provide a
very-low thermal-resistance path for heat removal from
the IC. The pad is electrical ground on the MAX3872
and should be soldered to the circuit board for proper
thermal and electrical performance.
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3872 high-speed inputs and outputs.
Power-supply decoupling should be placed as close to
V
input signals from the output signals. If a bare die is
used, mount the back of die to ground (GND) potential.
Multirate Clock and Data Recovery
with Limiting Amplifier
Figure 10. Interfacing with the MAX3861 AGC Using Threshold
Adjust
12
TIA OUTPUT
(2.488Gbps)
CC
REFERENCE CLOCK
______________________________________________________________________________________
as possible. To reduce feedthrough, isolate the
155.52MHz
AGC AMPLIFIER
Consecutive Identical Digits (CIDs)
MAX3861
R1 + R2 ≥ 50kΩ
+3.3V
R2
13
R1
0.82μF
Exposed Pad (EP) Package
- 1 PRBS with long runs of ones
SDI+
SDI-
SLBI+
SLBI-
V
V
CTRL
REF
SIS LREF
FIL
Layout Considerations
VCC_VCO
+3.3V
LOL
TTL
-10
CAZ-
MAX3872
RS1
0.1μF
. The CID tolerance
CAZ+
RS2
RATESET
+3.3V
VCC
FREFSET
SCLKO+
SCLKO-
+3.3V
SDO+
GND
SDO-
CML
CML
TRANSISTOR COUNT: 5142
PROCESS: SiGe BiPOLAR
SUBSTRATE: SOI
TOP VIEW
SLBI+
SLBI-
LREF
SDI+
SDI-
V
V
SIS
CC
CC
1
2
3
4
5
6
7
8
5mm x 5mm
MAX3872
QFN
Pin Configuration
Chip Information
24
23
22
21
20
19
18
17
VCC_OUT
SDO+
SDO-
VCC_OUT
SCLKO+
SCLKO-
VCC_VCO
RATESET

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