MAX3872EGJ Maxim Integrated Products, MAX3872EGJ Datasheet - Page 9

• Manufacturer Part Number: MAX3872EGJ
• Description: Timers & Support Products Multirate Clock and Data Recovery with L
• Manufacturer: Maxim Integrated Products

Specifications of MAX3872EGJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor (C
connected from FIL to VCC_VCO is required to set the
PLL damping ratio. Note that the PLL jitter bandwidth
does not change as the external capacitor changes,
but the jitter peaking, acquisition time, and loop stability
are affected. See the Design Procedure section for
guidelines on selecting this capacitor.
The loop filter output controls the two on-chip VCOs.
The VCOs provide low phase noise and are trimmed to
the frequency of 2.488GHz and 2.667GHz. The RATE-
SET pin is used to select the appropriate VCO. The
VCO output is connected to programmable dividers
controlled by inputs RS1 and RS2. See Tables 2 and 3
for the proper settings.
The LOL output indicates a PLL lock failure, either
because of excessive jitter present at the data input or
because of loss of input data. The LOL output is asserted
low when the PLL loses lock.
A DC-offset cancellation loop is implemented to remove
the DC offset of the limiting amplifier. To minimize the
low-frequency pattern-dependent jitter associated with
this DC-cancellation loop, the low-frequency cutoff is
10kHz (typ) with CAZ = 0.1µF, connected from CAZ+ to
CAZ-. The DC-offset cancellation loop operates only
when threshold adjust is disabled.
In applications in which the noise density is not bal-
anced between logical zeros and ones (i.e., optical
amplification using EDFA amplifiers), lower bit-error
ratios (BERs) can be achieved by adjusting the input
threshold. Varying the voltage at V
+2.1V achieves a vertical decision threshold adjust-
ment of +170mV to -170mV, respectively (Figure 2).
Use the provided bandgap reference voltage output
(V
DAC to set the voltage at V
generate the voltage for V
adjust is not required, disable it by connecting V
directly to V
REF
) with a voltage-divider circuit or the output of a
VCOs with Programmable Dividers
CC
and leave V
_______________________________________________________________________________________
DC-Offset Cancellation Loop
Decision Threshold Adjust
CTRL
REF
Design Procedure
CTRL
Multirate Clock and Data Recovery
floating.
(Figure 10). If threshold
. V
CTRL
REF
LOL Monitor
can be used to
from +0.3V to
Loop Filter
CTRL
FIL
)
The MAX3872 has three operational modes controlled
by the LREF and SIS inputs. The three operational
modes are normal, system loopback, and clock
holdover. Normal operation mode requires a serial data
stream at the SDI± input, system loopback mode
requires a serial data stream at the SLBI± input, and
clock holdover mode requires a reference clock signal
at the SLBI± inputs. See Table 1 for the required LREF
and SIS settings. Once an operational mode is chosen,
the remaining logic inputs (RATESET, RS1, RS2, and
FREFSET) program the input data rate or reference
clock frequency.
Three pins (RS1, RS2, and RATESET) are available for
setting the SDI± and SLBI± input to receive the appropri-
ate data rate. The FREFSET pin can be set to a zero or 1
while in normal or system loopback mode (Table 2).
Set the incoming reference clock frequency and outgoing
serial clock frequency by setting RS1, RS2, RATESET,
and FREFSET appropriately (Table 3).
with Limiting Amplifier
Table 1. Operational Modes
Table 2. Data Rate Settings
INPUT DATA RATE
1.25G/1.244G
2.488G/2.5G
666.51M
622.08M
166.63M
155.52M
2.667G
System loopback
(bps)
Clock holdover
Normal
MODE
Normal and System Loopback Settings
Clock Frequencies in Holdover Mode
RS1
0
0
1
0
0
1
1
RS2
Modes of Operation
0
0
1
1
1
0
0
LREF
RATESET
1
1
0
1
0
0
1
0
1
0
FREFSET
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
SIS
0
1
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