CY28400OC Silicon Laboratories Inc, CY28400OC Datasheet
CY28400OC
Specifications of CY28400OC
Available stocks
Related parts for CY28400OC
CY28400OC Summary of contents
Page 1
MHz Differential Buffer for PCI Express and SATA Features • CK409 or CK410 companion buffer • Four differential 0.7V clock pairs • Individual OE controls • Low CTC jitter (< 50 ps) • Programmable bandwidth • SRC_STOP# power management ...
Page 2
Pin Descriptions Pin Name 2,3 SRCT_IN, SRCC_IN 6,7,9,10,19,20,22,23 DIFT/C(2:1) & (6:5) 8,21 OE_1, OE_6 17 HIGH_BW# 16 SRC_STOP# 15 PWRDWN# 13 SCLK 14 SDATA 26 IREF 12 PLL/BYPASS# 28 VDD_A 27 VSS_A 4,25 VSS 1,5,11,18,24 VDD Serial Data Interface To ...
Page 3
Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description 20:27 Byte Count from master – 8 bits 28 Acknowledge from slave 29:36 Data byte 0 from master – 8 bits 37 Acknowledge from slave 38:45 ...
Page 4
Byte 0: Control Register 0 (continued) Bit @Pup Name 1 1 PLL/Bypass Byte 1: Control Register 1 Bit @Pup Name DIFT/ DIFT/ DIFT/ DIFT/C1 ...
Page 5
Byte 4: Vendor ID Register Bit @Pup Name Byte 5: Control Register 5 Bit @Pup Name ...
Page 6
PWRDWN#—Deassertion The power-up latency is less than 1 ms. This is the time from the deassertion of the PWRDWN# pin or the ramping of the power supply or the time from valid SRC_IN input clocks until the time that stable ...
Page 7
SRC_STOP# Clarification The SRC_STOP# signal is an active LOW input used for clean stopping and starting the DIF outputs (valid clock must be present on SRCT_IN). The SRC_STOP# signal is a de-bounced signal in that it’s state must remain unchanged ...
Page 8
SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 6. SRC_STOP# = Three-state, PWRDWN# = Driven SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 7. SRC_STOP# = Three-state, PWRDWN# = Three-state Output Enable Clarification The ...
Page 9
Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
Page 10
AC Electrical Specification (continued) Parameter Description ΔV Vcross Variation over all edges OX V Maximum Overshoot Voltage OVS V Minimum Undershoot Voltage UDS V Ring Back Voltage RB t Input to output skew in PLL mode PD(PLL) t Input to ...
Page 11
... V OVS V RB Figure 10. Single-ended Measurement Points for V Skew Management Point 0.000V Figure 11. Differential (Clock-CLock#) Measurement Points (Tperiod, Duty Cycle and Jitter) Ordering Information Ordering Code CY28400OC CY28400OCT Lead-free CY28400OXC CY28400OXCT Rev 1.0, November 21, 2006 LOW V UDS OVS T PERIOD High Duty Cycle % ...
Page 12
Package Drawing and Dimensions 28-Lead (5.3 mm) Shrunk Small Outline Package O28 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement ...