CY28400OC Silicon Laboratories Inc, CY28400OC Datasheet - Page 6

• Manufacturer Part Number: CY28400OC
• Description: Clock Buffer 100 MHz Diff Buffer PCI Express & SATA
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28400OC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
PWRDWN#—Deassertion
The power-up latency is less than 1 ms. This is the time from
the deassertion of the PWRDWN# pin or the ramping of the
power supply or the time from valid SRC_IN input clocks until
the time that stable clocks are output from the buffer chip (PLL
locked). If the control register PWRDWN# three-state bit is
programmed to ‘1’, all differential outputs will be driven HIGH
in less than 300 μs of PWRDWN# deassertion to a voltage
greater than 200 mV.
Table 4. Buffer Power-up State Machine
Notes:
2. The total power-up latency from power on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input).
3. If power is valid and PWRDWN# is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid input clocks
State
are detected, valid power, PWRDWN# deasserted with the PLL locked and stable are the DIF outputs enabled.
2
3
0
1
[3]
[2]
3.3V Buffer power off
After 3.3V supply is detected to rise above 1.8V–2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay
Buffer waits for a valid clock on the SRC_IN input and PWRDWN# deassertion
Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation
PWRDWN#
DIFC
DIFT
Power Off
>0.25ms
Delay
S1
S0
Figure 2. PWRDWN# Deassertion Diagram
Figure 3. Buffer Power-up State Diagram
<300uS, >200mV
Tdrive_Pwrdwn#
Tstable
<1mS
Description
PWRDWN# Asserted
No Input Clock
PWRDWN# De-
Wait for Input
Operation
Normal
assertion
Clock &
S3
S2
CY28400
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