SL28DB200AZI Silicon Laboratories Inc, SL28DB200AZI Datasheet - Page 3

• Manufacturer Part Number: SL28DB200AZI
• Description: Clock Generators & Support Products PCIe fam 1diff input 2 diff outputs
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28DB200AZI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Enable Clarification
OE# functionality allows for enabling and disabling individual
outputs. OE1# and OE2# are Active LOW inputs. Disabling the
outputs may be implemented by deasserting the OE# input
pin. If the OE# pin is deasserted, the output of interest will be
tri-stated. (The assertion and deassertion of this signal is
absolutely asynchronous.)
OE Assertion
All differential outputs that were tri-stated will resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2–6 SRC clock
periods. In addition, SRC clocks will be driven high within 15
ns of OE# assertion to a voltage greater than 200 mV
Absolute Maximum Conditions
DC Electrical Specifications
......................... Document #: 38-07722 Rev *C Page 3 of 8
VDD
VDDA
V
T
T
T
T
ESD
UL-94
MSL
VDDA
VDD
V
V
I
I
C
C
L
I
Parameter
Parameter
IL
IH
DD3.3V
S
A
A
J
IN
IN
IL
IH
IN
OUT
HBM
,
Core Supply Voltage
Analog Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
(Commercial Grade)
Temperature, Operating Ambient
(Industrial Grade)
Temperature, Junction
ESD Protection (Human Body Model)
Flammability Rating
Moisture Sensitivity Level
3.3V Operating Voltage
3.3V Input Low Voltage
3.3V Input High Voltage
Input Low Leakage Current
Input High Leakage Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Dynamic Supply Current
Description
Description
3.3 ± 5%
except internal pull-up resistors, 0 < V
except internal pull-down resistors, 0 < V
At max. load, Full Active, at 100MHz
Relative to V
Non-functional
Functional
Functional
Functional
JEDEC (JESD 22 - A114)
UL (Class)
OE Deassertion
The impact of deasserting OE# is that each corresponding
output will transition from normal operation to tri-state in a
glitch-free
deassertion to tri-stated outputs is between 2–6 DIF clock
periods.
Table 2. OE Functionality
Condition
Condition
SS
OE#
0
1
manner.
SRC,SRC#
Tri-State
Enable
IN
IN
< V
The
< V
DD
DD
2000
Min.
–0.5
–0.5
–0.5
–65
-40
0
maximum
V
SS
3.135
Min.
2.0
1.5
–5
–-
V–0
–
–
– 0.5
1
SL28DB200
V
DD
Max.
+150
V
150
latency
4.6
4.6
85
85
–
DD
+ 0.5
3.465
Max.
0.8
60
5
5
6
7
+ 0.5
from
VDC
Unit
°C
°C
°C
°C
Unit
V
V
V
mA
A
A
nH
pF
pF
V
V
V
the