Si5338D-A-GM Silicon Laboratories Inc, Si5338D-A-GM Datasheet - Page 26

• Manufacturer Part Number: Si5338D-A-GM
• Description: Clock Generators & Support Products I2C-PRGRMBL clock generatr 0.16-700MHz
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5338D-A-GM

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5338
3.10.4. Output Synchronization
Upon power up or a soft_reset the Si5338 synchronizes
the output clocks. With normal output polarity (no output
clock inversion), the Si5338 synchronizes the output
clocks to the falling, not rising edge. Synchronization at
the rising edge can be done by inverting all the clocks
that are to be synchronized.
3.10.5. Output R Divider
When the requested output frequency of a channel is
below 5 MHz, the Rn (n = 0,1,2,3) divider needs to be
set and enabled. This is automatically done in register
maps generated by the ClockBuilder Desktop. When
the Rn divider is active the step size range of the
frequency increment and decrement function will
decrease by the Rn divide ratio. The Rn divider can be
set to {1, 2, 4, 8, 16, 32}.
Non-unity settings of R0 will affect the Finc/Fdec step
size at the MultiSynth0 output. For example, if the
MultiSynth0 output step size is 2.56 MHz and R0 = 8,
the step size at the output of R0 will be 2.56 MHz
divided by 8 = .32 MHz. When the Rn divider is set to
non-unity, the initial phase offset of the CLKn output with
respect to other CLKn outputs is not guaranteed.
3.10.6. Zero-Delay Mode
The Si5338 supports an optional zero delay mode of
operation for applications that require minimal input-to-
output delay. In this mode, one of the device output
clocks is fed back to the feedback input pin (IN4 or IN5/
IN6) to implement an external feedback path which
nullifies the delay between the reference input and the
output clocks. Figure 15 shows the Si5338 in a typical
zero-delay configuration. It is generally recommended
that Clk3 be LVDS and that the feedback input be pins 5
and 6. For the differential input configuration to pins 5
and 6, see Figure 3 on page 17. The zero-delay mode
combined with the phase increment/decrement feature
allows unprecedented flexibility in generating clocks
with precise edge alignment.
26
Rev. 1.0
3.10.7. Spread Spectrum
To help reduce electromagnetic interference (EMI), the
Si5338 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread
energy across a broader range of frequencies, lowering
system EMI. The Si5338 implements spread spectrum
using its patented MultiSynth technology to achieve
previously unattainable precision in both modulation
rate and spreading magnitude as shown in Figure 16.
Through I
applied to any output clock, any clock frequency, and
any spread amount from ±0.1% to ±5% center spread
and –0.1% to –5% down spread.
The spreading rate is limited to 30 to 63 kHz.
The Spread Spectrum is generated digitally in the output
MultiSynths which means that the Spread Spectrum
parameters are virtually independent of process,
voltage and temperature variations. Since the Spread
Spectrum is created in the output MultiSynths, through
I
Spectrum parameters. Without the use of I
download only) the only supported Spread Spectrum
parameters are for PCI Express compliance composing
100 MHz clock, 31.5 kHz spreading frequency with the
choice of the spreading.
2
C each output channel can have independent Spread
Input
Clk
Figure 15. Si5338 in Zero Delay Clock
2
C control, the Spread spectrum can be
P1
P2
Generator Mode
PLL
Si5338
MS0
MS1
MS2
MS3
R0
R1
R2
R3
2
C (NVM
Clk0
Clk3
Clk1
Clk2