MAX3878EHJ Maxim Integrated Products, MAX3878EHJ Datasheet - Page 12

• Manufacturer Part Number: MAX3878EHJ
• Description: Timers & Support Products 2.5Gbps, +3.3V Clock and Data Retiming I
• Manufacturer: Maxim Integrated Products
• Type: Clock and Data Retimingr

Specifications of MAX3878EHJ

• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 163 mA
• Package / Case: TQFP-32 EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the received data amplitude is higher than
10mVp-p, the MAX3877/MAX3878 provide a typical jit-
ter tolerance of 0.64UI at jitter frequencies greater than
10MHz. The SDH/SONET jitter tolerance specification is
0.15UI, leaving a jitter allowance of 0.49UI for receiver
preamplifier and postamplifier design.
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
Figure 10. Interfacing with PECL Levels
12
Figure 11. CML Outputs
LEVELS
PECL
______________________________________________________________________________________
0.1µF
0.1µF
Jitter Tolerance and Input Sensitivity
25Ω
25Ω
MAX3877
100Ω
50Ω
SDI+
SDI-
V
V
CC
CC
MAX3877
50Ω
50Ω
50Ω
Trade-Offs
SDO+
SDO-
The BER is better than 1
greater than 4mVp-p. At 5mVp-p, jitter tolerance will be
degraded, but will still be above the SDH/SONET
requirement. The user can make a trade-off between jit-
ter tolerance and input sensitivity according to the spe-
cific application. Refer to Typical Operating
Characteristics for Jitter Tolerance and BER vs. Input
Amplitude.
When in holdover mode, the MAX3877/MAX3878 can
lock to an external reference clock to maintain a valid
clock output in the absence of input data. When LREF is
high, the PLL locks to an external 155.52MHz reference
clock, which is applied to the SLBI inputs. To enter
holdover mode automatically when there are no transi-
tions to the SDI inputs, LOS can be directly tied to LREF.
By maintaining frequency lock, the time required to re-
acquire lock is reduced.
The system loopback input may be used as an auxiliary
input for system loopback testing or as input for an exter-
nal 155.52MHz reference clock. When used as a loop-
back test, the user can connect a serializer output in a
transceiver directly to the SLBI inputs for system diag-
nostics. Using an external reference clock can maintain
PLL frequency lock in the absence of transitions on the
SDI inputs.
The MAX3877/MAX3878 have low frequency drift in the
absence of data transitions. As a result, long runs of con-
secutive zeros and ones can be tolerated while maintain-
ing a BER better than 1
tested using a 2
zeros to simulate the worst case. A CID tolerance of
2000 bits is typical.
The VCO frequency after 4096 bits (approximately 1.6µs)
may be estimated by using the VCO drift rate:
The exposed pad, 32-pin TQFP incorporates features
that provide a very low thermal-resistance path for heat
removal from the IC. The pad is electrical ground on the
MAX3877/MAX3878 and should be soldered to the cir-
cuit board for proper thermal and electrical performance.
f
=
=
2 488
2 488
.
.
GHz
GHz
Consecutive Identical Digits (CID)
Applications Information
13
±
±
10 21



- 1PRBS, substituting a long run of
1 65
Exposed Pad (EP) Package
.
.
kHz
µ ×
✕
s
10
✕
=
6 2
-10
.
10
µ
2 488
kHz
System Loopback
.
. The CID tolerance is
s
-10



Holdover Mode
GHz
for input signals
±
4 1
.
ppm