MAX3878EHJ Maxim Integrated Products, MAX3878EHJ Datasheet - Page 9

• Manufacturer Part Number: MAX3878EHJ
• Description: Timers & Support Products 2.5Gbps, +3.3V Clock and Data Retiming I
• Manufacturer: Maxim Integrated Products
• Type: Clock and Data Retimingr

Specifications of MAX3878EHJ

• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 163 mA
• Package / Case: TQFP-32 EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX3877/MAX3878 consist of a fully integrated
phase-locked loop (PLL), input amplifier, data retiming
block, and CML output buffer (MAX3877) or PECL out-
put buffer (MAX3878). The PLL consists of a phase/fre-
quency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO). Figure 5 shows the
functional diagram.
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
The SDI input amplifier accepts 2.488Gbps NRZ data
with differential input swing from 10mVp-p up to
1200mVp-p. The bit error rate is better than 1
input signals as small as 4mVp-p, though the jitter toler-
ance performance will be degraded. This amplifier
allows for adjustment of the input threshold level. For
interfacing with PECL signal levels, see Applications
Information, or refer to Applications Note HFAN 1.0,
Interfacing Between CML, PECL, and LVDS.
The SLBI input amplifier accepts either 2.488Gbps
loopback data or a 155MHz reference clock. This
amplifier accepts data with differential input swing from
Figure 5. Functional Diagram
THADJ
2.5Gbps, +3.3V Clock and Data Retiming ICs
SLBI+
SLBI-
LREF
SDI+
SDI-
SIS
_______________________________________________________________________________________
AMP
AMP
THRESHOLD
ADJUST
Detailed Description
V
CC
V
CC
SLBI Input Amplifier
SDI Input Amplifier
MUX
0
1
GND
CPWD+
CANCELLATION
DC-OFFSET/
DETECTOR
LOSS OF
PWD
SIGNAL
with Vertical Threshold Adjust
CPWD-
✕
10
LOS
-10
for
FREQUENCY
DETECTOR
PHASE &
50mVp-p up to 1200mVp-p. For interfacing with PECL
signal levels, see Applications Information.
The phase detector incorporated in the MAX3877 and
MAX3878 produces a voltage proportional to the phase
difference between the incoming data and the internal
clock. Because of its feedback nature, the PLL drives
the error voltage to zero, aligning the recovered clock
to the center of the incoming data eye for retiming.
The digital frequency detector (FD) aids frequency
acquisition during startup conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the in-phase and quadra-
ture VCO output on the rising edges of the data input
signal. The FD drives the VCO until the frequency dif-
ference is reduced to zero. Once frequency acquisition
is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequen-
cy detector.
While in holdover mode, a Type 4 phase/frequency
detector (PFD) is implemented to track the 155MHz ref-
erence clock signal. This PFD compares the incoming
155MHz reference clock with the divided down VCO
clock. The LREF input is used to enable holdover mode
(see Applications Information).
LOL
FIL+
FILTER
LOOP
/16
OR
/1
FIL-
D
VCO
Phase/Frequency Detector
Q
Φ
AMP
AMP
LOL
LOS
SDO+
SDO-
SCLKO+
SCLKO-
PHADJ
9