COM20020I3V-DZD-TR SMSC, COM20020I3V-DZD-TR Datasheet - Page 58

• Manufacturer Part Number: COM20020I3V-DZD-TR
• Description: Network Controller & Processor ICs 5Mbps ARCNET CTRL 2K x 8 ON-CHIP RAM
• Manufacturer: SMSC

Specifications of COM20020I3V-DZD-TR

• Mounting Style: SMD/SMT
• Package / Case: PLCC-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 12-05-06
A0-A2
D0-D7
nCS
nRD
nWR
*
Note 1:
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
**
T
T
T
T
Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
ARB
ARB
ARB
opr
t10
t1
t2
t3
t4
t5
t6
t7
t8
t9
t6 is measured from the latest active (valid) timing among nCS, nRD, A0-A2.
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Data Register requires a minimum of 5T
leading edge of the next nRD.
Data Register requires a minimum of 5T
leading edge of nRD.
nRD Low Width
nRD High Width
nWR
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
nRD High to Data High Impedance
opr
if SLOW ARB = 1
to nRD Low
Note 3
opr
t1
t10
if SLOW ARB = 0
CASE 2: RBUSTMG bit = 1
t3
Parameter
DATASHEET
t6
Page 58
VALID
ARB
ARB
from the trailing edge of nRD to the
from the trailing edge of nWR to the
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
t8
VALID DATA
t5
4T
ARB
min
-5
-5
100
0
0
30
20
0
*+30
60**
max
20
t7
t2
t4
units
t9
Note 2
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
SMSC COM20020I Rev D
Datasheet