CS8900A-IQ3R Cirrus Logic Inc, CS8900A-IQ3R Datasheet - Page 109
CS8900A-IQ3R
Manufacturer Part Number
CS8900A-IQ3R
Description
Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS8900A-CQZ.pdf
(138 pages)
Specifications of CS8900A-IQ3R
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DS271F5
The input pins not included in this test are:
After the Input Cycle is complete, one more cy-
cle of AEN returns all digital output pins and bi-
directional pins to a high-impedance state.
CS8900A
Crystal LAN™ Ethernet Controller
SD08-SD15 27-24, 21-18 SD0 - SD7 65-68, 71-74
Pin Name
Pin Name
DMACK1
DMACK0
MEMW
MEMR
TEST
AEN
Dl+
Cl+
Dl-
Pin #
Table 41.
Pin #
14
16
28
29
63
76
79
80
81
Table 42.
(continued)
Pin Name
Pin Name
RESET
SLEEP
IOW
XTAL1
IOR
RXD+
RXD-
Cl-
CIRRUS LOGIC PRODUCT DATASHEET
Pin #
Pin #
61
62
75
77
82
91
92
97
6.2.3 Continuity Cycle
The combination of a complete Output Cycle,
a complete Input Cycle, and an additional AEN
cycle is called a Continuity Cycle. Each Conti-
nuity Cycle lasts for 85 AEN clock cycles. The
first Continuity Cycle can be followed by addi-
tional Continuity Cycles by keeping TEST low
and continuing to cycle AEN. When TEST is
driven high, the CS8900A exits Boundary
Scan mode and AEN is again used as the ISA-
bus Address Enable.
Figure 32 shows a complete Boundary Scan
Continuity Cycle.
Figure 33 shows Boundary Scan timing.
109
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