CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet
CS8900A-IQ3ZR
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CS8900A-IQ3ZR Summary of contents
Page 1
... Ethernet controllers. The CS8900A includes on-chip RAM, 10BASE-T transmit and receive filters, and a direct ISA-Bus interface with 24 mA Drivers. In addition to high integration, the CS8900A offers a broad range of performance features and configura- tionoptions. automatically adapts to changing network traffic pat- terns and available system resources ...
Page 2
... Checking EEPROM for presence of Reset Configuration Block ..........23 3.4.3.5 Determining Number of Bytes in the Reset Configuration Block .........23 3.4.4 Groups of Configuration Data .............................................................................23 3.4.4.1 Group Header ......................................................................................23 3.4.5 Reset Configuration Block Checksum ................................................................24 3.4.6 EEPROM Example .............................................................................................24 3.4.7 EEPROM Read-out ............................................................................................24 2 .............................................................................................................12 CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller DS271F5 ...
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... EEPROM Command Execution ......................................................................... 25 3.5.3 Enabling Access to the EEPROM ...................................................................... 26 3.5.4 Writing and Erasing the EEPROM ..................................................................... 26 3.6 Boot PROM Operation .................................................................................................... 26 3.6.1 Accessing the Boot PROM ................................................................................. 26 3.6.2 Configuring the CS8900A for Boot PROM Operation ........................................ 26 3.7 Low-Power Modes ..........................................................................................................27 3.7.1 Hardware Standby ..............................................................................................27 3.7.2 Hardware Suspend ............................................................................................. 27 3.7.3 Software Suspend ..............................................................................................27 3 ...
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... Accesses in Memory Mode .................................................................................73 4.9.2 Configuring the CS8900A for Memory Mode ......................................................74 4.9.3 Basic Memory Mode Transmit ............................................................................74 4.9.4 Basic Memory Mode Receive .............................................................................75 4.9.5 Polling the CS8900A in Memory Mode ...............................................................75 4.10 I/O Space Operation ......................................................................................................75 4.10.1 Receive/Transmit Data Ports 0 and 1 ...............................................................75 4 CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ ...
Page 5
... I/O Mode Operation .......................................................................................... 76 4.10.8 Basic I/O Mode Transmit .................................................................................. 76 4.10.9 Basic I/O Mode Receive ................................................................................... 77 4.10.10 Accessing Internal Registers .......................................................................... 77 4.10.11 Polling the CS8900A in I/O Mode ................................................................... 77 5.0 OPERATION .......................................................................................................................... 78 5.1 Managing Interrupts and Servicing the Interrupt Status Queue ...................................... 78 5.2 Basic Receive Operation ................................................................................................. 78 5.2.0.1 Overview ............................................................................................. 78 5 ...
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... Overview .............................................................................................................94 5.4.2 Configuring the CS8900A for Auto-Switch DMA .................................................94 5.4.3 Auto-Switch DMA Operation ...............................................................................94 5.4.4 DMA Channel Speed vs. Missed Frames ...........................................................95 5.4.5 Exit From DMA ...................................................................................................96 5.4.6 Auto-Switch DMA Example .................................................................................96 5.5 StreamTransfer ...............................................................................................................96 5.5.1 Overview .............................................................................................................96 5.5.2 Configuring the CS8900A for StreamTransfer ....................................................96 5.5.3 StreamTransfer Operation ..................................................................................96 5.5.4 Keeping StreamTransfer Mode Active ................................................................98 5 ...
Page 7
... CS8900A Crystal LAN™ Ethernet Controller Release Date PP1 NOV 1997 Preliminary Release, revision 1 PP2 DEC 1998 Preliminary Release, revision 2 PP3 MAR 1999 Preliminary Release, revision 3 PP4 APR 2001 Preliminary Release, revision 4 Page 13: INTRQ[0:2] changed to INTRQ[0..3] Page 41: Added bit definitions for Revisions C and D ...
Page 8
... The AUI port provides a direct interface to 10BASE-2, 10BASE-5, and 10BASE-FL net- works, and is capable of driving a full 50-meter AUI cable. 1.2 System Applications The CS8900A is designed to work well in ei- ther motherboard or adapter applications. 1.2.1 Motherboard LANs The CS8900A requires the minimum number of external components needed for a full Ethernet node ...
Page 9
... RJ-45 CS8900A Switch DMA options, make it an excellent choice for high-performance, low-cost ISA adapter cards (Figure 2). The CS8900A’s wide range of configuration options and perfor- mance features allow engineers to design Ethernet solutions that meet their particular system requirements. Adapter card design op- tions include: • ...
Page 10
... The serial EEPROM port, used for configu- ration and initialization, eliminates the need for expensive switches and jumpers. • The CS8900A is designed to be used on a 2-layer circuit board instead of a more ex- pensive multilayer board. • The 8900A-based solution offers the small- est footprint available, saving valuable printed circuit board area ...
Page 11
... T c Figure 3. Typical ISA Bus Connection Diagram DS271F5 4.99 k Ω 4.7 k Ω SLEEP TEST RES 2 92 RXD- 91 RXD TXD- 87 TXD CS8900A 84 DO- 83 DO+ 82 CI- 81 CI+ 80 DI- 79 DI+ 39.2 Ω BSTATUS/HCI 680 Ω 100 LANLED 680 Ω 99 LINKLED 17 CSOUT Boot-PROM 27C256 20 CE ...
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... DMARQ0 15 DMACK0 16 CSOUT 17 SD15 18 SD14 19 SD13 20 SD12 21 DVDD2 22 DVSS2 23 SD11 24 SD10 25 12 CS8900A 100-pin TQFP (Q) Top View CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller 75 RESET 74 SD7 73 SD6 72 SD5 71 SD4 70 DVSS4 69 DVDD4 68 SD3 67 SD2 66 SD1 65 SD0 64 IOCHRDY AEN 63 62 ...
Page 13
... AEN - Address Enable, Input PIN 63. When TEST is high, this active-high input indicates to the CS8900A that the system DMA controller has control of the ISA bus. When AEN is high, the CS8900A will not perform slave I/O space operations. When TEST is low, this pin becomes the shift clock input for the Boundary Scan Test ...
Page 14
... IOW - I/O Write, Input PIN 62. When IOW is low and a valid address is detected, the CS8900A writes the data on the System Data Bus into the selected 16-bit I/O register. IOW is ignored if REFRESH is low. IOCS16 - I/O Chip Select 16-bit, Open Drain Output PIN 33. ...
Page 15
... EEPROM. When TEST is low, this pin becomes the output for the Boundary Scan Test. CSOUT - Chip Select for External Boot PROM, PIN 17. Active-low output used to select an external Boot PROM when the CS8900A decodes a valid Boot PROM memory address. 10BASE-T Interface TXD+/TXD- - 10BASE-T Transmit, Differential Output Pair PINS 87 and 88. ...
Page 16
... When the HCE0 bit of the Self Control register (Register 15) is clear, this active-low output is low when the CS8900A detects the presence of valid link pulses. When the HC0E bit is set, the host may drive this pin low by setting the HCBO in the Self Control register ...
Page 17
... Address, Source Address, Length field and LLC data (all supplied by the host). If the frame is less than 64 bytes, including CRC, the CS8900A adds pad bits if configured to do so. Finally, the CS8900A appends the proper 32- bit CRC value. The Section 5.6 on page 99 provides a de- tailed description of packet transmission ...
Page 18
... I/O address on the ISA System Address bus (SA0 - SA15) through must match the address space of the CS8900A. For a Read, IOR must be low, and for a Write, IOW must be low. For additional information about I/O Mode, see Section 4.10 on page 75. ...
Page 19
... Power-Down Reset If the supply voltage drops below approximate- ly 2.5 V, there is a chip-wide reset. The CS8900A comes out of reset once the power supply returns to a level greater than approxi- mately 2.5 V and the crystal oscillator has sta- bilized. 3.3.1.4 EEPROM Reset There is a chip-wide reset if an EEPROM checksum error is detected (see Section 3 ...
Page 20
... Allowing Time for Reset Operation After a reset, the CS8900A goes through a self configuration. This includes calibrating on-chip analog circuitry, and reading EEPROM for va- lidity and configuration. Time required for the reset calibration is typically 10 ms. Software drivers should not access registers internal to the CS8900A during this time ...
Page 21
... Reset Configuration Block The first block in EEPROM, referred to as the Reset Configuration Block, is used to automat- ically program the CS8900A with an initial con- figuration after a reset. Additional user data 64 may also be stored in the EEPROM if space is 64 available ...
Page 22
... It can be divided into three logi- cal sections: a header, one or more groups of configuration data words, and a checksum val- ue. All of the words in the Reset Configuration Block are read sequentially by the CS8900A after each reset, starting with the header and 22 Configuration Block Header. ...
Page 23
... EEPROM EEPROM is attached but not used for con- figuration, Crystal recommends that the high byte of the first word be programmed with 00h in order to ensure that the CS8900A will not at- tempt to read configuration data from the EE- PROM. 3.4.3.5 Determining Number of Bytes in the ...
Page 24
... EEPROM Read-out If the EEDI pin is asserted high at the end of reset, the CS8900A reads the first word of EE- PROM data by: 1) Asserting EECS 2) Clocking out a Read-Register-00h com- 24 ...
Page 25
... EEPROM or reset to default configura- tion) the INITD bit is set (Register 16, SelfST, bit 7). 3.5 Programming the EEPROM After initialization, the host can access the EE- PROM through the CS8900A by writing one of seven commands to the EEPROM Command Command Opcode (bits 9,8) Read Register ...
Page 26
... CS8900A, into the EEPROM. If the command is a Write, the data in the EEPROM Data register (PacketPage base + 0042h) fol- lows. If the command is a Read, the data in the specified EEPROM location is written into the EEPROM Data register ...
Page 27
... During CS8900A uses the least amount of current of the three low-power modes. All internal circuits are turned off and the CS8900A’s core is elec- tronically isolated from the rest of the system. Accesses from the ISA bus and Ethernet activ- ity are both ignored. ...
Page 28
... To exit SW Suspend, the host must write to the CS8900A’s assigned I/O space (the Write is only used to wake the CS8900A, the Write itself is ignored). Upon exit, the CS8900A per- forms a complete reset, and then goes through a normal initialization procedure. CS8900A Configuration ...
Page 29
... CS8900A or the host. When controlled by the CS8900A, LINKLED is low whenever the CS8900A receives valid 10BASE-T link puls- es. To configure this pin for CS8900A control, the HC0E bit (Register 15, SelfCTL, Bit C) must be clear. When controlled by the host, LINKLED is low whenever the HCB0 bit (Reg- ister 15, SelfCTL, Bit E) is set ...
Page 30
... Frame Check Sequence (FCS). The data after the SFD and before the FCS (Destination Ad- dress, Source Address, Length, and data field) is supplied by the host. FCS generation by the CS8900A may be disabled by setting the In- hibitCRC bit (Register 9, TxCMD, bit C). Figure 9 shows the Ethernet frame format. 3.9.2.2 Reception ...
Page 31
... Transmit Command. If the JabberiE bit (Regis- ter 7, TxCFG, Bit A) is set, the host is interrupt- ed. A Jabber condition indicates that there may be something wrong with the CS8900A transmit function. To prevent possible network faults, the host should clear the transmit buf- fer. Possible options include: Reset the chip with either software or hard- ware reset (see Section 3 ...
Page 32
... Two primary tasks of the MAC are to avoid net- work collisions, and then recover from them when they occur. In addition, when the CS8900A is using the AUI, the MAC must sup- port the SQE Test function described in sec- tion 7.2.4.6 of the Ethernet standard. ...
Page 33
... CS8900A Crystal LAN™ Ethernet Controller attempting transmission. The CS8900A sup- ports two schemes for determining when to ini- tiate transmission: Two-Part Deferral, and Simple Deferral. Selection of the deferral scheme is determined by the 2-partDefDis bit (Register 13, LineCTL, Bit D). If the 2-partDef- Dis bit is clear, the MAC uses a two-part defer- ral process defined in section 4 ...
Page 34
... Collision Resolution If a collision is detected while the CS8900A is transmitting, the MAC responds in one of three ways depending on whether normal col- lision (within the first 512 bits of transmission late collision (after the first 512 bits of transmission): 3.9.5.5 Normal Collisions If a collision is detected before the end of the ...
Page 35
... TestCTL, Bit B). When disabled, the CS8900A only waits the 9.6 µs IPG time before starting transmission. 3.9.5.10 SQE Test If the CS8900A is transmitting on the AUI, the external transceiver should generate an SQE Test signal on the CI+/CI- pair following each Carrier Sense ...
Page 36
... Ether- net standard (ISO/IEC 8802-3, 1993). It in- cludes all analog and digital circuitry needed to interface the CS8900A directly to a simple iso- lation transformer page 121 for a connection diagram). Figure 13 provides a block diagram of the 10BASE-T transceiver ...
Page 37
... MAC) RXSQL RX ENDEC TX 3.11.1 10BASE-T Filters The CS8900A’s 10BASE-T transceiver in- cludes integrated low-pass transmit and re- ceive filters, eliminating the need for external filters or a filter/transformer hybrid. On-chip fil- ters are gm/c implementations of fifth-order Butterworth low-pass filters. Internal tuning cir- ...
Page 38
... LoRxSquelch bit (Register 13, LineCTL, Bit E). 3.11.4 Link Pulse Detection To prevent disruption of network operation due to a faulty link segment, the CS8900A continu- ally monitors the 10BASE-T receive pair (RXD+/ RXD-) for packets and link pulses. Af- ter each packet or link pulse is received, an in- ternal Link-Loss timer is started ...
Page 39
... The AUI transmitter is a differential driver de- signed to drive a 78 Ω cable. It accepts data from the ENDEC and transmits it directly on the DO+/DO- pins. After transmission has started, the CS8900A expects to see the pack- et “looped-back” (or echoed) to the receiver, causing the Carrier Sense signal to be assert- DS271F5 ...
Page 40
... External Clock Oscillator A 20-MHz quartz crystal or CMOS clock input is required by the CS8900A CMOS clock input is used, it should be connected the to XTAL1 pin, with the XTAL2 pin left open. The 40 clock signal should be 20 MHz ±0.01% with a duty cycle between 40% and 60%. The speci- fications for the crystal are described in Section 7 ...
Page 41
... Bus Interface Registers The Bus Interface registers are used to config- ure the CS8900A’s ISA-bus interface and to map the CS8900A into the host system’s I/O and Memory space. Most of these registers are written only during initialization, remaining unchanged while the CS8900A is in normal operating mode ...
Page 42
... Status and Control Registers Notes: 1. All registers are accessed as words only. 2. Read operation from the reserved location provides undefined data. Writing to a reserved location or undefined bits may result in unpredictable operation of the CS8900A. 42 0400h) and one transmit frame (starting at PacketPage base + 0A00h) are directly acces- sible ...
Page 43
... Write-only Transmit Frame Location Notes: 1. All registers are accessed as words only. 2. Read operation from the reserved location provides undefined data. Writing to a reserved location or undefined bits may result in unpredictable operation of the CS8900A. Table 13. PacketPage Memory Address Map DS271F5 Description (2 bytes per register) ...
Page 44
... The Product Identification Code Register is located in the first four bytes of the PacketPage (0000h to 0003h). The register contains a unique 32-bit product ID code that identifies the chip as a CS8900A. The host can use this num- ber to determine which software driver to load and to check which features are available. ...
Page 45
... See Section 3.2 on page 18 and Section 5.3 on page 90. After reset EEPROM is found by the CS8900A, then the register has the following initial state which corre- sponds to setting all DMRQ pins to high-impedance EEPROM is found, then the register's initial value may be set by the EEPROM ...
Page 46
... Memory Base Address: The lower three bytes (002Ch, 002Dh, and 002Eh) are used for the 20-bit memory base address. The upper three nibbles are reserved. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
Page 47
... See Section 3.6 on page 26. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: XXXX XXXX XXXX 0000 0000 0000 0000 0000 4 ...
Page 48
... See Section 5.2.9 on page 86. Reset value is: XXXX XXXX XXXX XXXX 48 Least significant byte of the EEPROM data. Least significant byte of the byte count. CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller Address 0042h Address 0050h DS271F5 ...
Page 49
... Status and Event Registers Status and Event registers report the status of transmitted and received frames, as well as in- formation about the configuration of the CS8900A. They are read-only and are desig- nated by even numbers (e.g. Register 2, Reg- ister 4, etc.). The Interrupt Status Queue (ISQ special type of Status/Event register ...
Page 50
... Section 4.4.4 on page 51 provides a detailed description of the bits in each register. 4.4.3.1 Act-Once Bits There are four bits that cause the CS8900A to take a certain action only once when set. These “Act-Once” bits are: Skip_1 (Register 3, RxCFG, Bit 6), RESET (Register 15, SelfCTL, Bit 6), ResetRxDMA (Register 17, BusCTL, Bit 6), and SWint-X (Register B, BufCFG, Bit 6) ...
Page 51
... There are nine Accept bits located in the Rx- CTL register (Register 5), each of which is fol- lowed by the suffix A. Accept bits indicate which types of frames will be accepted by the CS8900A. (A frame is said to be “accepted” by DS271F5 the CS8900A when the frame data are placed in either on-chip memory host memory by DMA ...
Page 52
... AUI/10B T HWStan HW SW Sus- dbyE SleepE pend DMA Memo- UseSA DMAex- Burst ryE tend Disable AUIloop ENDEC Backoff loop CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller Register Number (Offset (0102h) Promis IAHa- 5 cuousA shA (0104h) Loss-of- 7 riE CRSiE ...
Page 53
... The Interrupt Status Queue Register is used in both Memory Mode and I/O Mode to provide the host with interrupt information. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s) in one of five registers, maps the contents of that register to the ISQ register, and drives an IRQ pin high. Three of the registers mapped to ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEvent (Register C) ...
Page 54
... The operation of this bit is independent of the received packet integrity (good or bad CRC). After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
Page 55
... CS8900A Crystal LAN™ Ethernet Controller 4.4.7 Register 4: Receiver Event (RxEvent, Read-only, Address: PacketPage base + 0124h Dribblebits IAHash F E Extradata Runt Alternate meaning if bits 8 and 9 are both set (see Section 5.2.10 on page 87 for exception regarding Broadcast frames Dribblebits IAHash F E Hash Table Index (see Section 5.2.10 on page 87) RxEvent reports the status of the current received frame ...
Page 56
... The CS8900A accepts only the first 1518 bytes and ignores the rest. When clear, frames longer than 1518 bytes are discarded. See Note 5. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 5.2.10 on page 87. ...
Page 57
... CS8900A stops attempting to transmit that packet. When this bit is set, there is an interrupt upon detecting the 16th collision. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
Page 58
... TxCFG, Bit 6) is set, there is an interrupt. SQEerror At the end of a transmission on the AUI, the CS8900A expects to see a collision within 64 bit times. If this does not happen, there is an SQE error and this bit is set. If SQEerroriE (Register 7, TxCFG, Bit 7) is set, there is an interrupt. ...
Page 59
... If InhibitCRC is clear, the CS8900A appends the CRC. If InhibitCRC is set, the CS8900A does not append the CRC After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
Page 60
... BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent changes from RxDest to Rx128. After reset EEPROM is found by the CS8900A, then the register has the following initial state after reset EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
Page 61
... CS8900A Crystal LAN™ Ethernet Controller TxUnderrun This bit is set if CS8900A runs out of data before it reaches the end of the frame (called a trans- mit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an interrupt. RxMiss If set, one or more receive frames have been lost due to slow movement of data out of the re- ceive buffers ...
Page 62
... LoRx Squelch 2-part DefDis LineCTL determines the configuration of the MAC engine and physical interface. 010011 These bits provide an internal address used by the CS8900A to identify this as the Line Control Register. SerRxON When set, the receiver is enabled. When clear, no incoming packets pass through the receiver. ...
Page 63
... After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
Page 64
... HC1 is high. HC1 may drive an LED or a logic gate. When HC1E (Bit D) is clear, this con- trol bit is ignored. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
Page 65
... Status Register. When reading this register, these bits will be 010110, where the LSB corre- sponds to Bit 0. 3,3VActive If the CS8900A is operating on a 3.3V supply, this bit is set. If the CS8900A is operating supply, this bit is clear. INITD If set, the CS8900A initialization, including read-in of the EEPROM, is complete. ...
Page 66
... When cleared, the CS8900A will not generate any interrupts. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
Page 67
... E FDX TestCTL controls the diagnostic test modes of the CS8900A. 011001 These bits provide an internal address used by the CS8900A to identify this as the Test Control Register. DisableLT When set, the 10BASE-T interface allows packet transmission and reception regardless of the link status. DisableLT is used in conjunction with the LinkOK (Register 14, LineST, Bit 7) as fol- ...
Page 68
... This bit must be set when performing loopback tests on the 10BASE-T port. When clear, the CS8900A is configured for standard half-duplex 10BASE-T operation. At reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
Page 69
... When TxPadDis is clear, if the host gives a transmit length less than 60 bytes and InhibitCRC is set, then the CS8900A pads to 60 bytes. If the host gives a transmit length less than 60 bytes and InhibitCRC is clear, then the CS8900A pads to 60 bytes and appends the CRC. ...
Page 70
... TxPadDis and InhibitCRC bits in the TxCMD register. See Table 36, and Section 5.6 on page 99. TxLength must be >3 and < 1519. Since this register is write-only, it’s initial state after reset is undefined. 70 CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller DS271F5 ...
Page 71
... The value of this register must be loaded from external storage, for example, from the EEPROM. See Section 3.3 on page 19. If the CS8900A is not able to load the IA from the EEPROM, then after a reset this register is undefined, and the driver must write an address to this register. ...
Page 72
... Memory writes using REP MOVS to the TxFrame location. See Section 5.6 on page 99. 4.8 Eight and Sixteen Bit Transfers A data transfer to or from the CS8900A can be done in either I/O or Memory space, and can be either 16 bits wide (word transfers bits wide (byte transfers). Because the CS8900A’s internal architecture is based on a 16-bit data bus, word transfers are the most efficient ...
Page 73
... The block must start at an X000h boundary, with the PacketPage base address mapped to X000h. When the CS8900A comes out of re- set, its default configuration is I/O Mode. Once Memory Mode is selected (by setting the Memory E bit (BusCTL Register)), all of the CS8900A’ ...
Page 74
... The other method limits memory mapping to the first 1 Mbyte of host memory space. General Memory Mode Operation: Configuring the CS8900A so that its internal memory can be mapped anywhere within host Memory space requires the following: • a simple circuit must be added to decode the Latchable Address bus (LA20 - LA23) and the BALE signal ...
Page 75
... Receive/Transmit Data Ports 0 and 1 These two ports are used when transferring transmit data to the CS8900A and receive data from the CS8900A. Port 0 is used for 16- bit operations and Ports 0 and 1 are used for 32-bit operations (lower-order word in Port 0). 4.10.2 TxCMD Port ...
Page 76
... Page Pointer. 4.10.6 PacketPage Data Ports 0 and 1 The PacketPage Data Ports are used to trans- fer data to and from any of the CS8900A's in- ternal registers. Port 0 is used for 16-bit operations and Port 0 and 1 are used for 32-bit operations (lower-order word in Port 0). ...
Page 77
... BufCFG, Bit 8) is set, the host will be inter- rupted when Rdy4Tx (Register C, BufE- vent, Bit 8) becomes set. If the TxBidErr bit (Register 18, BusST, Bit 7) is set, the trans- mit length is not valid. 3) Once the CS8900A is ready to accept the frame, the host executes repetitive write in- structions (REP OUT) ...
Page 78
... Section 4.3 on page 44. An event triggers an interrupt only when the EnableIRQ bit of the Bus Control register (bit F of register 17) is set. After the CS8900A has generated an interrupt, the first read of the ISQ makes the INTRQ output pin go low (inactive). ...
Page 79
... CS8900A Crystal LAN™ Ethernet Controller An enabled interrupt occurs. The selected interrupt request pin is driven high (active) if not already high. The host reads the ISQ. The selected interrupt request pin is driven low. EXIT. Yes Interrupts re-enabled. (Interrupts will be disabled for at least 1 ...
Page 80
... Transfer Yes The term "transfer" refers to moving data across the ISA bus, to and from the CS8900A. During receive operations, only frame data are transferred from the CS8900A to the host (the preamble and SFD are stripped off by the Host Reads CS8900A's MAC engine) ...
Page 81
... Choosing which Frame Types to Ac- cept The RxCTL register (Register 5) is used to de- termine which frame types will be accepted by the CS8900A (a receive frame is said to be "accepted" when the frame is buffered, either on chip or in host memory via DMA). Table 20 describes the configuration bits in this register. ...
Page 82
... Bit B) is set as soon as the first 128 bytes of the incoming frame have been re- ceived. If the Rx128iE bit (Register B, Buf- CFG, bit B) is set, the CS8900A generates a corresponding interrupt. Once the Rx128 bit is set, the RxDest bit is cleared and the host is allowed to read the first 128 bytes of the incoming frame ...
Page 83
... Like all Event bits, RxDest and Rx128 are set by the CS8900A whenever the appropriate event occurs. Unlike other Event bits, RxDest and Rx128 may be cleared by the CS8900A without host intervention. All other event bits are cleared only by the host reading the appro- priate event register, either directly or through the Interrupt Status Queue (ISQ) ...
Page 84
... EOF No Received? Yes EOF No Received? Yes Figure 22. Early Interrupt Generation CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller RxDest cleared and Runt set. If RuntA is set, frame accepted and Host may read frame. RxDest cleared and RxOK or CRCerror set, as appropriate. ...
Page 85
... BufEvent register (Register C), either directly or through the ISQ. When the CS8900A commits buffer space to a particular held receive frame (termed a com- mitted received frame), no data from subse- quent frames can be written to that buffer space until the frame is freed from commit- ment ...
Page 86
... I/O or memory modes, and by dedicating the CPU to reading this counter, and using the count to read the frame out of the CS8900A at the same time it is being received by the CS8900A from the Ethernet (parallel frame-reception and frame-read-out tasks). ...
Page 87
... Receive Frame Address Filtering The CS8900A is equipped with a Destination Address (DA) filter used to determine which receive frames will be accepted. (A receive frame is said to be "accepted" by the CS8900A when the frame data are placed in either on- chip memory host memory by DMA). The DA filter can be configured to accept the fol- lowing frame types: 5 ...
Page 88
... Address at PacketPage base + 0158h, if necessary. 3) Set SerRxON to re-enable the receiver. Because the receiver has been disabled, the CS8900A will ignore frames while the host is changing the DA filter. 5.2.12 Hash Filter The hash filter is used to help determine which Multicast frames and which Individual Address frames should be accepted by the CS8900A ...
Page 89
... RxEvent contains a normal RxEvent, else RxEvent contained a hash RxEvent. Contents of RxEvent Bits F-A Hash Table Index Hash table index (MSB) CS8900A CRC Logic 6-to-64 decoder 1 64-bit Logical Address Filter (LAF) Written into PacketPage base + 150h Figure 23. Hash Filter Operation ...
Page 90
... RxDMAonly bit (Register 3, RxCFG, Bit 9). Note: If the RxDMAonly bit and the AutoRxD- MAE bit (Register 3, RxCFG, Bit A) are both All receive set, then RxDMAonly takes precedence, and the CS8900A is in DMA mode for all receive frames. PacketPage Address 0024h 0026h Table 27 ...
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... DMA since the last read-out of this register. Table 27. Receive DMA Registers 5.3.3 DMA Receive Buffer Size In receive DMA mode, the CS8900A stores re- ceived frames (along with their status and length circular buffer located in host mem- ory space. The size of the circular buffer is de- termined by the RxDMAsize bit (Register 17, BusCTL, Bit D) ...
Page 92
... RxDMAFrame Bit The RxDMAFrame bit (Register C, BufEvent, bit 7) is controlled by the CS8900A and is set whenever the value in the DMA Frame Count register is non-zero. The host cannot clear Rx- DMAFrame by reading the BufEvent register (Register C) ...
Page 93
... DMA. The software driver should maintain a PDMA_START) that will point to the beginning of a new frame. After the CS8900A is initial- ized and before any frame is received, pointer PDMA_START points to the beginning of the DMA buffer memory area. The first read of the DMA Buffer Base Address " ...
Page 94
... DMA if necessary. Note that if the AutoRxDMAE bit and the RxD- MAonly bit (Register 3, RxCFG, bit 9) are both set, the CS8900A uses DMA for all receive frames. 5.4.3 Auto-Switch DMA Operation Whenever a frame begins to be received in ...
Page 95
... Auto-Switch DMA works only on entire re- ceived frames. The CS8900A does not use Auto-Switch DMA to transfer partial frames. Also, when a frame has been committed (see Section 5.2.5 on page 85), the CS8900A will not switch to DMA mode until the committed frame has been transferred completely or skipped. ...
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... The CS8900A is not in the process of transferring a frame via DMA. 5.4.6 Auto-Switch DMA Example Figure 27 shows how the CS8900A enters and exits Auto-Switch DMA mode. 5.5 StreamTransfer 5.5.1 Overview The CS8900A supports an optional feature, StreamTransfer, that can reduce the amount of CPU overhead associated with frame re- ception ...
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... DMA Frame Count (PacketPage base + 0028h) is zero. Frame 1 received and completely stored in on-chip RAM. Frame 2 received and completely stored in on-chip RAM. At this point, the CS8900A does not have sufficient buffer space for another complete large frame (1518 bytes). Frame 3 starts to be received and passes the DA filter. ...
Page 98
... RxDMAFrame bit (Register C, BufEvent, Bit 7); and, • generates an RxDMAFrame interrupt. 5.5.4 Keeping StreamTransfer Mode Active When the CS8900A initiates a StreamTransfer cycle, it will continue to execute cycles as long as the following conditions hold true: • all packets received are of legal length with valid CRC; ...
Page 99
... CS8900A's buffer memory. The first phase begins with the host issuing a Transmit Command. This informs the CS8900A that a frame transmitted and tells the chip when (i.e. after 5, 381, or 1021 bytes have been transferred or after the full frame has been transferred to the CS8900A) and how the frame should be sent (i ...
Page 100
... D 2-part When set, two-part deferral is DefDis disabled. Table 31. Physical Interface Configuration Note that the CS8900A transmits in 10BASE- T mode when no link pulses are being re- ceived only if bit DisableLT is set in register Test Control (Register 19). 5.6.2.2 Selecting which Events Cause Inter- rupts The TxCFG register (Register 7) and the Buf- ...
Page 101
... TxLength register (PacketPage base + 0146h). 3) The host must read the BusST register (Register 18) The information written to the TxCMD register tells the CS8900A how to transmit the next DS271F5 frame. The bits that must be programmed in the TxCMD register are described in Table 35. Bit ...
Page 102
... CS8900A waits for the next interrupt. If Rdy4Tx is set, then the CS8900A is ready to accept the frame. 4) When the CS8900A is ready to accept the frame, the host transfers the entire frame from host memory to CS8900A memory using REP instruction (REP MOVS to ...
Page 103
... Buffer Space to Transmit Frame Host Writes Transmit Frame to CS8900A CS8900A Transmits Frame Exit Transmit Process ister 8, TxEvent, Bit 8). If the TxOKiE bit (Reg- ister 7, TxCFG, bit 8) is set, the CS8900A generates a corresponding interrupt. CIRRUS LOGIC PRODUCT DATASHEET Transmit Request Polling Loop 103 ...
Page 104
... Process other events that caused interrupt 5.6.9 Rdy4TxNOW vs. Rdy4Tx The Rdy4TxNOW bit (Register 18, BusST, bit 8) is used to tell the host that the CS8900A is ready to accept a frame for transmission. This bit is used during the Transmit Request pro- 104 Enter Packet Transmit Process ...
Page 105
... If there is, the CS8900A sets the Rdy4TxNOW bit. If not, and the Rdy4TxiE bit is set, the CS8900A waits for buffer space to free up and then sets the Rdy4Tx bit. If Rdy4TxiE is not set, the CS8900A sets the Rdy4TxNOW bit when space becomes avail- able ...
Page 106
... Send without pads and without CRC Notes the TxPadDis bit is clear and InhibitCRC is set and the CS8900A is commanded to send a frame of length less than 60 bytes, the CS8900A pads. 9. The CS8900A will not send a frame with TxLength less than 3 bytes. 106 If the hub is attempting to auto-negotiate with the CS8900A, the CS8900A will never get more than 1 " ...
Page 107
... Crystal LAN™ Ethernet Controller 6.0 TEST 6.1 TEST MODES 6.1.1 Loopback & Collision Diagnostic Tests Internal and external Loopback and Collision tests can be used to verify the CS8900A's functionality when configured 10BASE-T or AUI operation. 6.1.2 Internal Tests Internal tests allow the major digital functions to be tested, independent of the analog func- tions ...
Page 108
... Boundary Scan will check to see if the orienta- tion of the chip is correct, and if there are any open or short circuits. Boundary Scan is controlled by the TEST pin. When TEST is high, the CS8900A is config- ured for normal operation. When TEST is low, the following occurs: • ...
Page 109
... Cycle lasts for 85 AEN clock cycles. The first Continuity Cycle can be followed by addi- tional Continuity Cycles by keeping TEST low and continuing to cycle AEN. When TEST is Pin # driven high, the CS8900A exits Boundary 82 Scan mode and AEN is again used as the ISA bus Address Enable ...
Page 110
... Figure 32. Boundary Scan Continuity Cycle 110 Not in Boundary Scan Test Mode TEST switches low (AEN must be low) ENTER BOUNDARY SCAN: CS8900A resets, all digital output pins and bi-directional pins enter High-Z state, and AEN becomes shift clock AEN switches high AEN switches low ...
Page 111
... CS8900A Crystal LAN™ Ethernet Controller TESTSEL AEN Outputs All outputs tri-state EEDataOut OUTPUTS Hi Z DS271F5 LINKLED LANLED BSTATUS low low low SLEEP OUTPUT TEST 34 Clocks COMPLETE CONTINUITY CYCLE 85 Clocks Figure 33. Boundary Scan Timing CIRRUS LOGIC PRODUCT DATASHEET RESET ELCS copied ...
Page 112
... Power Supply CS8900A-CQ, -CQZ & -IQ, -IQZ 3.3V Power Supply CS8900A-CQ3, -CQ3Z & -IQ3, -IQ3Z Operating Ambient Temperature CS8900A-CQ, -CQZ & -CQ3, -CQ3Z Operating Ambient Temperature CS8900A-IQ, -IQZ & -IQ3, -IQ3Z 7.3 DC CHARACTERISTICS Parameter Crystal (when using external clock - square wave) ...
Page 113
... CS8900A Crystal LAN™ Ethernet Controller DC CHARACTERISTICS Parameter Digital Inputs and Outputs Power Supply Current while Active 5.0V Power Supply Current while Active 3.3V Output Low Voltage Output Low Voltage (all outputs) V Output High Voltage ≤ V Output Leakage Current OUT Input Low Voltage Input High Voltage 0 ≤ ...
Page 114
... IOR2 t IOR6 t IOR3 Valid Data Figure 34. 16-Bit I/O Read, IOCHRDY not used Valid Address t IOR7 t IOR8 Valid Data t IOR9 Figure 35. 16-Bit I/O Read, with IOCHRDY CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller = 5 VDD = 3.3V) Min Typ Max - - 135 0 - ...
Page 115
... CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter 16-Bit Memory Read, IOCHRDY Not Used SA [19:0], SBHE, CHIPSEL, active to MEMCS16 low Address, SBHE, CHIPSEL active to MEMR active MEMR low to SD valid Address, SBHE, CHIPSEL hold after MEMR inactive MEMR inactive to SD 3-state ...
Page 116
... DMA3 DMA4 Valid Valid Data Data Figure 38. 16-Bit DMA Read Valid Address t IOW1 t IOW7 IOW6 IOW2 IOW3 t IOW4 t IOW5 Valid Data In Figure 39. 16-Bit I/O Write CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller Min Typ Max 135 - 110 ...
Page 117
... CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter 16-Bit Memory Write Address, SBHE, CHIPSEL valid to MEMCS16 low Address, SBHE, CHIPSEL valid to MEMW low MEMW pulse width MEMW low to SD valid SD hold after MEMW high Address hold after MEMW inactive MEMW inactive to active 10BASE-T Transmit TXD Pair Jitter into 100 Ω ...
Page 118
... TRX1 t TRX2 t TRX3 t TRX4 t TRX5 t LN1 t LN2 t LN3 t LN4 t LN5 t LN6 t TRX4 Figure 42. 10BASE-T Receive t LN2 t LN3 t LN4 Figure 43. 10BASE-T Link Integrity CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller Min Typ Max - - ±13 ±13.5 - 540 - 270 - 100 200 ...
Page 119
... CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter AUI Transmit DO Pair Rise and Fall Times DO Pair Jitter at Bit Cell Center DO Pair Positive Hold Time at Start of Idle DO Pair Return to ≤ 40 mVp after Last Positive Transition AUI Receive DI Pair Rise and Fall Time ...
Page 120
... BPROM1 t BPROM2 t BPROM3 t SKS t CCS t DIS t DIH CSH BPROM1 t BPROM2 Figure 47. External Boot PROM Access t SKS t CSS t DIH t DIS t DH Figure 48. EEPROM CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller Min Typ Max Unit 100 - - 250 - - 250 - - 500 - - 100 ...
Page 121
... The Rt and Rr resistors are ±1% tolerance. The CS8900A supports 100, 120, and 150 Ω unshielded twisted pair cables. The proper val- • ues of Rt and Rr, for a given cable impedance, are shown below: Cable Impedance (Ω) ...
Page 122
... Motional Crystal Capacitance Series Resistance Shunt Capacitance 122 39.2 Ω 39.2 Ω 39.2 Ω 39.2 Ω ( MHz quartz crystal is used, it must meet the fol- Min - -50 - CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller DB15 +12 V Typ Max Unit 20 - MHz - +50 ...
Page 123
... Power Supply CS8900A-CQ, -CQZ & -IQ, -IQZ 3.3V Power Supply CS8900A-CQ3, CQ3Z & -IQ3, -IQ3Z Operating Ambient Temperature CS8900A-CQ, -CQZ & -CQ3, -CQ3Z Operating Ambient Temperature CS8900A-IQ, -IQZ & -IQ3, -IQ3Z 8.3 DC CHARACTERISTICS Parameter Crystal (when using external clock - square wave) ...
Page 124
... T = >70° B24 V OH B4w, O24ts, O4 ≤ OD24, OD10, B24, O24ts B4w ≤ ISQ V SQL V AOD V AODU V IDLE V AISQ CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller Min Typ Max Unit - 0 0 0.4 0.425 0 -20 ...
Page 125
... CS8900A Crystal LAN™ Ethernet Controller 8.4 SWITCHING CHARACTERISTICS Parameter 16-Bit I/O Read, IOCHRDY Not Used Address, AEN, SBHE active to IOCS16 low Address, AEN, SBHE active to IOR active IOR low to SD valid Address, AEN, SBHE hold after IOR inactive IOR inactive to active ...
Page 126
... MEMR5 t MEMR6 t MEMR7 t MEMR8 t MEMR9 Valid Address t MEMR1 t MEMR4 t t MEMR6 MEMR2 t t MEMR3 MEMR5 Valid Data Valid Address t MEMR7 t MEMR8 Valid Data t MEMR9 CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller Min Typ Max Unit - - 135 125 - 175 - - ...
Page 127
... CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter DMA Read DMACKx active to IOR active AEN active to IOR active IOR active to Data Valid IOR inactive to SD 3-state IOR n-1 high to DMARQx inactive DMACKx, AEN hold after IOR high 16-Bit I/O Write ...
Page 128
... MEMW6 t MEMW7 t TTX1 t TTX2 t TTX3 Valid Address t t MEMW1 MEMW6 MEMW2 MEMW7 MEMW3 t MEMW5 t MEMW4 Valid Data In Figure 55. 16-Bit Memory Write t TTX1 Figure 56. 10BASE-T Transmit CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller Min Typ Max Unit - - 110 - - - - ...
Page 129
... CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter 10BASE-T Receive Allowable Received Jitter at Bit Cell Center Allowable Received Jitter at Bit Cell Boundary Carrier Sense Assertion Delay Invalid Preamble Bits after Assertion of Carrier Sense Carrier Sense Deassertion Delay 10BASE-T Link Integrity ...
Page 130
... ARX4 t ARX5 t ACL1 t ACL2 t ACL3 t ACL4 t ACL5 ATX2 Figure 59. AUI Transmit ARX2 t ARX4 Figure 60. AUI Receive t ACL1 t t ACL2 ACL2 Figure 61. AUI Collision CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller Min Typ Max Unit - 0 250 - - 6 ± 240 - - 200 ...
Page 131
... CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter External Boot PROM Access Address active to MEMR MEMR active to CSOUT low MEMR inactive to CSOUT high EEPROM EESK Setup time relative to EECS EECS/ELCS_b Setup time wrt ↑ EESK EEDataOut Setup time wrt ↑ EESK EEDataOut Hold time wrt ↑ ...
Page 132
... The Rt and Rr resistors are ±1% tolerance. The CS8900A supports 100, 120, and 150 Ω unshielded twisted pair cables. The proper val- • ues of Rt and Rr, for a given cable impedance, are shown below: Cable Impedance (Ω) ...
Page 133
... CS8900A Crystal LAN™ Ethernet Controller 8.6 AUI WIRING CS8900A Col 8.7 QUARTZ CRYSTAL REQUIREMENTS lowing specifications) Parameter Parallel Resonant Frequency Resonant Frequency Error ( pF) L Resonant Frequency Change Over Operating Temperature Crystal Capacitance Motional Crystal Capacitance Series Resistance Shunt Capacitance DS271F5 ...
Page 134
... JEDEC Designation: MS026 134 MILLIMETERS DIM MIN A --- A1 0. 0.45 ∝ 0.00° CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller A A1 NOM MAX 1.60 0.15 0.22 0.27 16.00 14.00 16.00 14.00 0.50 0.60 0.75 7.00° DS271F5 ...
Page 135
... CS8900A Crystal LAN™ Ethernet Controller 10.0 GLOSSARY OF TERMS 10.1 Acronyms AUI Attachment Unit Interface CRC Cyclic Redundancy Check CS Carrier Sense CSMA/CD Carrier Sense Multiple Access with Collision Detection DA Destination Address EEPROM Electrically Erasable Programmable Read Only Memory EOF End-of-Frame FCS ...
Page 136
... Time required for an Ethernet Frame to cross a maximum length Ethernet network. One Slot Time equals 512 bit times. Transmit Collision A transmit collision occurs when the receive inputs, RXD+/RXD- (10BASE-T) or CI+/CI- (AUI) are active while a packet is being transmitted. 136 CIRRUS LOGIC PRODUCT DATASHEET CS8900A Crystal LAN™ Ethernet Controller DS271F5 ...
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... TxEvent 10.4 Definitions Specific to the CS8900A Act-Once bit A control bit that causes the CS8900A to take a certain action once when a logic "1" is written to that bit. To cause the action again, the host must rewrite a "1". Committed Receive Frame A receive frame is said to be "committed" after the frame has been buffered by the CS8900A, and the host has been notified, but the frame has not yet been transferred by the host ...
Page 138
... Standby A feature of the CS8900A used to conserve power. When in Standby mode, the CS8900A can be awakened either by 10BASE-T activity or host command. Suspend A feature of the CS8900A used to conserve power. When in Suspend mode, the CS8900A can be awakened only by host command. Transfer The term "transfer" refers to moving frame data across the ISA bus to or from the CS8900A ...