CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 63

• Manufacturer Part Number: CS8900A-IQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
2-partDefDis
LoRxSquelch
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM
is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: 0000 0000 0001 0011
4.4.17 Register 14: Line Status
(LineST, Read-only, Address: PacketPage base + 0134h)
LineST reports the status of the Ethernet physical interface.
010100
LinkOK
AUI
10BT
PolarityOK
CRS
Reset value is: 0000 0000 0001 0100
CS8900A
Crystal LAN™ Ethernet Controller
LinkOK
7
F
CRS
DefDis bit clear, the CS8900A uses the standard two-part deferral as defined in ISO/IEC 8802-
3 paragraph 4.2.3.2.1. With the 2-partDefDis bit set, the two-part deferral is disabled.
8802-3 specification. When set, the thresholds are reduced by approximately 6dB. This is use-
ful for operating with "quiet" cables that are longer than 100 meters.
Register. When reading this register, these bits will be 010100, where the LSB corresponds to
Bit 0.
CS8900A has just come out of reset, or because the receiver has not detected any activity (link
pulses or received packets) for at least 50 ms.
the polarity is reversed. If PolarityDis (Register 13, LineCTL, Bit C) is clear, the polarity is auto-
matically corrected, if needed. The PolarityOK status bit shows the true state of the incoming
polarity independent of the PolarityDis control bit. Thus, if PolarityDis is clear and PolarityOK is
clear, then the receive polarity is inverted, and corrected.
received. CRS remains asserted until the end of frame (EOF). At EOF, CRS goes inactive in
about 1.3 to 2.3 bit times after the last low-to-high transition of the recovered data.
Before a transmission can begin, the CS8900A follows a deferral procedure. With the 2-part-
When clear, the 10BASE-T receiver squelch thresholds are set to levels defined by the ISO/IEC
These bits provide an internal address used by the CS8900A to identify this as the Line Status
If set, the 10BASE-T link has not failed. When clear, the link has failed, either because the
If set, the CS8900A is using the AUI.
If set, the CS8900A is using the 10BASE-T interface.
If set, the polarity of the 10BASE-T receive signal (at the RXD+ / RXD- inputs) is correct. If clear,
This bit tells the host the status of an incoming frame. If CRS is set, a frame is currently being
E
6
D
5
CIRRUS LOGIC PRODUCT DATASHEET
PolarityOK
C
4
B
3
010100
A
2
10BT
1
9
AUI
0
8
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