CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 51

• Manufacturer Part Number: CS8900A-IQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
4.4.3.4 Accept Bits
There are nine Accept bits located in the Rx-
CTL register (Register 5), each of which is fol-
lowed by the suffix A. Accept bits indicate
which types of frames will be accepted by the
CS8900A. (A frame is said to be “accepted” by
CS8900A
Crystal LAN™ Ethernet Controller
Out-of-windowiE (TxCFG) Out-of-window (TxEvent)
Loss-of-CRSiE (TxCFG)
TxUnderruniE (BufCFG)
TxColOvfloiE (BufCFG)
MissOvfloiE (BufCFG)
ExtradataiE (RxCFG)
CRCerroriE (RxCFG)
Interrupt Enable Bit
SQEerroriE (TxCFG)
Rdy4TxiE (BufCFG)
RxDMAiE (BufCFG)
RxDestiE (BufCFG)
RxMissiE (BufCFG)
AnycolliE (TxCFG)
Rx128iE (BufCFG)
JabberiE (TxCFG)
RxOKiE (RxCFG)
16colliE (TxCFG)
TxOKiE (TxCFG)
(register name)
RuntiE (RxCFG)
Table 15. Interrupt Enable Bits and Events
TxCOL counter overflows
RxDMAFrame (BufEvent)
“Number-of Tx-collisions”
Loss-of-CRS (TxEvent)
TxUnderrun (BufEvent)
counter is incremented
RxMISS counter over-
Event Bit or Counter
Extradata (RxEvent)
CRCerror (RxEvent)
SQEerror (TxEvent)
RxMISS (BufEvent)
Rdy4Tx (BufEvent)
RxDest (BufEvent)
Rx128 (BufEvent)
Jabber (TxEvent)
RxOK (RxEvent)
TxOK (TXEvent)
(register name)
16coll (TxEvent)
flows past 1FFh
Runt (RxEvent)
CIRRUS LOGIC PRODUCT DATASHEET
past 1FFh
(TxEvent)
the CS8900A when the frame data are placed
in either on-chip memory, or in host memory
by DMA.) Four of these bits have correspond-
ing Interrupt Enable (iE) bits. An Accept bit and
an Interrupt Enable bit are independent opera-
tions. It is possible to set either, neither, or
both bits. The four corresponding pairs of bits
are:
If one of the above Interrupt Enable bits is set
and the corresponding Accept bit is clear, the
CS8900A generates an interrupt when the as-
sociated receive event occurs, but then does
not accept the receive frame (the length of the
receive frame is set to zero).
The other five Accept bits in RxCTL are used
for
Section 5.2.10 on page 87). The Accept
mechanism is explained in more detail in
Section 5.2 on page 78.
4.4.4 Status and Control Register Sum-
mary
The table on the following page (Table 16) pro-
vides a summary of the Status and Control
registers. Section 4.4.4 on page 51 gives a de-
tailed description of each Status and Control
register.
IE Bit in RxCFG
destination
CRCerroriE
ExtradataiE
RxOKiE
RuntiE
address
A Bit in RxCTL
CRCerrorA
ExtradataA
filtering
RxOKA
RuntA
(see
51