CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 74

• Manufacturer Part Number: CS8900A-IQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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4.9.2 Configuring the CS8900A for Mem-
ory Mode
There are two different methods of configuring
the CS8900A for Memory Mode operation.
One method allows the CS8900A's internal
memory to be mapped anywhere within the
host system's 24-bit memory space. The other
method limits memory mapping to the first 1
Mbyte of host memory space.
General Memory Mode Operation: Configuring
the CS8900A so that its internal memory can
be mapped anywhere within host Memory
space requires the following:
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The address on the ISA System Address
bus (SA0 - SA19) is within the Memory
space range of the CS8900A or Boot
PROM.
The CHIPSEL input pin is low.
Either the MEMR pin or the MEMW pin is
low.
a simple circuit must be added to decode
the Latchable Address bus (LA20 - LA23)
and the BALE signal.
the host must configure the external logic
with the correct address range as follows:
1) Check to see if the INITD bit (Register
2) Check to see if the ELpresent bit (Reg-
3) Set the ELSEL bit of the EEPROM
4) Configure the external logic serially.
16,SelfST, bit 7) is set, indicating that
initialization is complete.
ister 16, SelfST, bit B) is set. This bit in-
dicates that external logic for the LA
bus decode is present.
Command Register to activate the
ELCS pin for use with the external de-
code circuit.
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Limiting Memory Mode to the First 1 Mbyte of
Host
CS8900A so that its internal memory can be
mapped only within the first 1 Mbyte of host
memory space requires the following:
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4.9.3 Basic Memory Mode Transmit
Memory Mode transmit operations occur in the
following order (using interrupts):
1) The host bids for storage of the frame by
2) The host reads the BusST register (Regis-
the host must write the memory base ad-
dress into the Memory Base Address reg-
ister (PacketPage base + 002Ch);
the host must set the MemoryE bit (Regis-
ter 17, BusCTL, Bit A); and
the host must set the UseSA bit (Register
17, BusCTL, Bit 9).
the CHIPSEL pin must be tied low;
the ISA-bus SMEMR signal must be con-
nected to the MEMR pin;
the ISA-bus SMEMW signal must be con-
nected to the MEMW pin;
the host must write the memory base ad-
dress into the Memory Base Address reg-
ister (PacketPage base + 002Ch);
the host must set the MemoryE bit (Regis-
ter 17, BusCTL, Bit A); and
the host must clear the UseSA bit (Register
17, BusCTL, Bit 9).
writing the Transmit Command to the TxC-
MD register (memory base + 0144h) and
the transmit frame length to the TxLength
register (memory base + 0146h). If the
transmit length is erroneous, the command
is discarded and the TxBidErr bit (Register
18, BusST, Bit 7) is set.
ter 18, memory base + 0138h). If the
Rdy4TxNOW bit (Bit 8) is set, the frame
Memory
Crystal LAN™ Ethernet Controller
Space:
Configuring
CS8900A
DS271F5
the