ispGDX160V-5B272 Lattice, ispGDX160V-5B272 Datasheet

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ispGDX160V-5B272

Manufacturer Part Number
ispGDX160V-5B272
Description
Analog & Digital Crosspoint ICs USE ispGDX2
Manufacturer
Lattice
Datasheet

Specifications of ispGDX160V-5B272

Maximum Dual Supply Voltage
3.6 V
Minimum Dual Supply Voltage
2.3 V, 3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
2.5 V, 3.3 V
Supply Type
Dual
Configuration
Programmable
Package / Case
BGA-272
Input Level
TTL
Output Level
TTL
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ispGDX
June 2010
Product Change Notification (PCN) #09-10 has been issued to discontinue select devices
in this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
ispGDX160VA
Product Line
ispGDX160V
Select Devices Discontinued!
5555 N.E. Moore Ct.
®
160V/VA Device Datasheet
ispGDX160V-5B272
ispGDX160V-7B272
ispGDX160V-5B208
ispGDX160V-7B208
ispGDX160V-5Q208
ispGDX160V-7Q208
ispGDX160V-7Q208I
ispGDX160VA-3B272
ispGDX160VA-5B272
ispGDX160VA-7B272
ispGDX160VA-5B272I
ispGDX160VA-7B272I
ispGDX160VA-9B272I
ispGDX160VA-3Q208
ispGDX160VA-5Q208
ispGDX160VA-7Q208
ispGDX160VA-5Q208I
ispGDX160VA-7Q208I
ispGDX160VA-9Q208I
ispGDX160VA-3B208
ispGDX160VA-3BN208
ispGDX160VA-5B208
ispGDX160VA-5BN208
ispGDX160VA-7B208
ispGDX160VA-7BN208
ispGDX160VA-5B208I
ispGDX160VA-5BN208I
ispGDX160VA-7B208I
ispGDX160VA-7BN208I
ispGDX160VA-9B208I
ispGDX160VA-9BN208I
Ordering Part Number
Hillsboro, Oregon 97124-6421
Internet: http://www.latticesemi.com
Phone (503) 268-8000
Active / Orderable
Active / Orderable
Product Status
Discontinued
Discontinued
FAX (503) 268-8347
Reference PCN
PCN#09-10
PCN#09-10

Related parts for ispGDX160V-5B272

ispGDX160V-5B272 Summary of contents

Page 1

... Product Change Notification (PCN) #09-10 has been issued to discontinue select devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number ispGDX160V-5B272 ispGDX160V-7B272 ispGDX160V-5B208 ispGDX160V-7B208 ispGDX160V ispGDX160V-5Q208 ...

Page 2

... LEAD-FREE PACKAGE OPTIONS * “VA” Version Only Copyright © 2004 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...

Page 3

... I/Os. ** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and CLKEN3 respectively in all devices. Specifications ispGDX160V/VA In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. That is, any I/O pin configured as an input can drive one or more I/O pins configured as outputs ...

Page 4

... I/O Cell 79 160 Input GRP 80 I/O Cells Inputs Vertical Outputs Horizontal Specifications ispGDX160V/VA The various I/O pin sets are also shown in the block diagram below. The and D I/O pins are grouped together with one group per side. I/O Architecture Each I/O cell contains a 4:1 dynamic MUX controlled by ...

Page 5

... MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable for each I/O cell MUX. These expansion inputs share the same path as the standard and D MUX inputs, and Specifications ispGDX160V/VA allow adjacent I/O cell outputs to be directly connected without passing through the global routing pool. The ...

Page 6

... B22 B21 fanout delays and has PCI compatible drive capability. D15 D14 D16 D15 Only the ispGDX160VA is available in the fastest (3.5ns) Commercial speed grade and in -5,-7, and -9ns Industrial D17 D16 grades in all packages. D18 D17 D21 ...

Page 7

... Decoders Buffers / Registers Data Path System Bus #2 Clock(s) Specifications ispGDX160V/VA Programmable Switch Replacement (PSR) Includes solid-state replacement and integration of me- chanical DIP Switch and jumper functions. Through in-system programming, pins of the ispGDXV/VA de- vices can be driven to HIGH or LOW logic levels to emulate the traditional device outputs. PSR functions do not require any input pin connections ...

Page 8

... OE3 Port #4 OE4 Note: All OE and SEL lines driven by external arbiter logic (not shown). Specifications ispGDX160V/VA Designing with the ispGDXV/VA As mentioned earlier, this architecture satisfies the PRSI class of applications without restrictions: any I/O pin as a single input or bidirectional can drive any other I/O pin as ...

Page 9

... I/O Reference Voltage CCIO o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C I/O Capacitance 1 C Dedicated Clock Capacitance 2 Erase/Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispGDX160VA 1 0°C to +70°C Commercial -40°C to +85°C Industrial A PACKAGE TYPE TYPICAL PQFP BGA, fpBGA PQFP BGA, fpBGA MINIMUM 10,000 8 MIN ...

Page 10

... I/O Reference Voltage CCIO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. I/O voltage configuration must be set to VCC. Specifications ispGDX160VA Figure 8. Test Load GND to V CCIO(MIN) < 1.5ns 10 CCIO(MIN CCIO(MIN) See Figure 8 Device Output * C L includes Test Fixture and Probe Capacitance ...

Page 11

... An input driving four I/O cells at 40MHz results in a dynamic I 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. Specifications ispGDX160VA 1 Over Recommended Operating Conditions CONDITION – ...

Page 12

... Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. Specifications ispGDX160VA Over Recommended Operating Conditions DESCRIPTION 1 ...

Page 13

... Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. Specifications ispGDX160VA Over Recommended Operating Conditions DESCRIPTION 1 ...

Page 14

... External Timing Parameters (Continued) ispGDX160VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas ispGDX160VA Maximum Specifications ispGDX160VA apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1) ...

Page 15

... Global Reset t 65 Global Reset to I/O Register Latch gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. Specifications ispGDX160VA 1 Over Recommended Operating Conditions 1 DESCRIPTION MIN. MAX. MIN. MAX. UNITS — ...

Page 16

... Global Reset t 65 Global Reset to I/O Register Latch gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. Specifications ispGDX160VA 1 Over Recommended Operating Conditions 1 DESCRIPTION MIN. MAX. MIN. MAX. UNITS — ...

Page 17

... Typical 100mV of input hysteresis. o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C I/O Capacitance 1 C Dedicated Clock Capacitance 2 Erase/Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispGDX160V 1,2 PARAMETER Commercial T = 0°C to +70°C A Industrial T = -40°C to +85°C A TYPICAL MINIMUM 10,000 16 MIN. MAX. 3.0 3 ...

Page 18

... An input driving four I/O cells at 40 MHz results in a dynamic I 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bidirectionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. Specifications ispGDX160V GND to 3.0V ≤ 1.5ns 10% to 90% 1 ...

Page 19

... Reset Pulse Width Output Delay Adder for Output Timings Using Slow Slew Rate Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except Specifications ispGDX160V Over Recommended Operating Conditions DESCRIPTION 1 ( tsu3+tgco1 ...

Page 20

... External Timing Parameters (Continued) ispGDX160V timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas ispGDX160V Maximum Specifications ispGDX160V apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1) ...

Page 21

... Global Reset t 65 Global Reset to I/O Register Latch gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. Specifications ispGDX160V 1 Over Recommended Operating Conditions 1 DESCRIPTION MIN. MAX. MIN. MAX. UNITS — ...

Page 22

... Timing Model OE MUX Expander Input MUX0 MUX1 GRP tgrp #33 CLKEN tioclkeg #64 CLK tioclk #60 Y0,1,2,3 tgclk #61 Y0,1,2,3, Enable Specifications ispGDX160V/VA DATA (I/O INPUT) CLK REGISTERED I/O OUTPUT CLKEN t en RESET wl REGISTERED I/O OUTPUT tgoe #58 tmuxd #34 tmuxs #36 tmuxio #37 tmuxg #38 MUX Expander Output ...

Page 23

... TCK EPEN ispGDX 160V/VA Device Specifications ispGDX160V/VA signals are fed into the on-chip programming circuitry where a state machine controls the programming. On-chip programming can be accomplished using an IEEE 1149.1 boundary scan protocol. The IEEE 1149.1- compliant interface signals are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS) control ...

Page 24

... Table 3. I/O Shift Register Order DEVICE TDI, TOE, Y2, Y3, RESET, Y1, Y0, I/O B20 .. B39, I C39, I D19, I/O B19 .. B0, ispGDX160V/VA I/O A39.. A0, I/O D39 .. D20, TDO Table 4. ispGDX160V/VA Device ID Codes DEVICE 32-BIT BOUNDARY SCAN ID CODE ispGDX160V 0000, 0000, 0011, 0101, 0011, 0000, 0100, 0011 ...

Page 25

... Figure 11. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN (from previous Shift DR Clock DR Figure 12. Boundary Scan State Machine Test-Logic-Reset 1 0 Run-Test/Idle 0 Specifications ispGDX160V/VA Downlowad (ispDCD™), ispCODE ‘C’ routines or any third-party programmers. Contact Lattice Technical Sup- port to obtain more detailed programming information cell 1 1 Select-DR-Scan 0 1 ...

Page 26

... BSCAN test Capture register hold time t btuco BSCAN test Update reg, falling edge of clock to valid output t btuoz BSCAN test Update reg, falling edge of clock to output disable t btuov BSCAN test Update reg, falling edge of clock to output enable Specifications ispGDX160V/ btsu bth T btcl ...

Page 27

... If the optional output voltage is not required, this pin must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply Connect pins are not to be connected to any active signals, VCC or GND. 2. “VA” version only. Specifications ispGDX160V/VA Description 26 ...

Page 28

... VCC 1, 17, 33, 49, 65, 89, 105, 1 121, 137, 153, 156 , 170, 184, 193 VCCIO 156 1 NC 73, 74, 179 1. VCC on ispGDX160V, VCCIO on ispGDX160VA. Specifications ispGDX160V/VA 208-Ball fpBGA D9 A12 A8 D10 N8 V10 R8 Y10 B9 C11 C9 ...

Page 29

... I/O Locations: ispGDX160V/VA (Ordered by I/O Signal Name and 208-Pin PQFP Location) I/O Control 208 208 272 Signal Signal PQFP fpBGA BGA VCC I/O A0 CLK/CLKEN I/O A2 MUXsel1 4 C2 I/O A3 MUXsel2 5 A1 GND I/O A4 CLK/CLKEN I/O A6 MUXsel1 9 D2 I/O A7 MUXsel2 10 D1 ...

Page 30

... I/O Locations: ispGDX160V/VA (Ordered by 208-Ball BGA Location) I/O Control 208 208 272 Signal Signal PQFP fpBGA BGA I/O A3 MUXsel2 5 A1 I/O D39 MUXsel2 208 A2 I/O D36 CLK/CLKEN 205 A3 I/O D33 OE 201 A4 I/O D30 MUXsel1 198 A5 I/O D27 MUXsel2 194 A6 I/O D23 ...

Page 31

... I/O Locations: ispGDX160V/VA (Ordered by 272-Ball BGA Location) I/O Control 208 208 272 Signal Signal PQFP fpBGA BGA I/O D36 CLK/CLKEN 205 A3 A3 I/O D34 MUXsel1 202 B4 A4 I/O D30 MUXsel1 198 A5 A5 I/O D24 CLK/CLKEN 190 C7 A8 I/O D20 CLK/CLKEN 186 ...

Page 32

... B38 B35 B32 B28 I/O I/O I/O I B39 B33 B29 B27 NCs are not to be connected to any active signals, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. Specifications ispGDX160V/ I/O I/O I/O Y3/ 1 D16 TOE NC 1 D13 D20 D24 CLKEN3 I/O I/O I/O NC ...

Page 33

... B36 B33 B31 I/O I/O I/O I/O I/O T B38 B37 B34 B32 B29 NCs are not to be connected to any active signals, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. Specifications ispGDX160V/ I/O I/O 1 EPEN RESET NC D17 D23 D27 I/O I/O I/O I/O Y2/ ...

Page 34

... OE I MUXsel1 I MUXsel2 I — VCC 49 50 CLK/CLKEN I I MUXsel1 I Connect Pins (NC) are not to be connected to any active signal, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. Specifications ispGDX160V/VA ispGDX160V/VA Top View 33 Data Control 2 156 VCCIO/VCC — 155 I 154 I CLK/CLKEN 153 VCC — 152 ...

Page 35

... BN208 = Lead-Free 208-Ball fpBGA B272 = 272-Ball BGA COMMERCIAL ORDERING NUMBER ispGDX160VA-3Q208 ispGDX160VA-3B208 ispGDX160VA-3B272 ispGDX160VA-5Q208 ispGDX160VA-5B208 ispGDX160VA-5B272 ispGDX160VA-7Q208 ispGDX160VA-7B208 ispGDX160VA-7B272 ispGDX160V-5Q208 ispGDX160V-5B208 ispGDX160V-5B272 ispGDX160V-7Q208 ispGDX160V-7B208 ispGDX160V-7B272 34 0212/ispGDXVA PACKAGE 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA 208-Pin PQFP 208-Ball fpBGA ...

Page 36

... FAMILY tpd (ns) 3.5 ispGDXVA 5 7 FAMILY tpd (ns) 5 ispGDXVA 7 9 Note: The ispGDX160VA devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, e.g. ispGDX160VA-3B208-5I. Specifications ispGDX160V/VA INDUSTRIAL ORDERING NUMBER ispGDX160VA-5Q208I ispGDX160VA-5B208I ispGDX160VA-5B272I ispGDX160VA-7Q208I ispGDX160VA-7B208I ispGDX160VA-7B272I ispGDX160VA-9Q208I ...

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